diff for duplicates of <1366760770.5825.17@snotra> diff --git a/a/1.txt b/N1/1.txt index 6b75ca8..5c50b92 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,34 +1,34 @@ On 04/19/2013 05:47:34 AM, Zhao Chenhui wrote: > These cache operations support Freescale SoCs based on BOOK3E. > Move L1 cache operations to fsl_booke_cache.S in order to maintain -> easily. And, add cache operations for backside L2 cache and platform =20 +> easily. And, add cache operations for backside L2 cache and platform > cache. ->=20 -> The backside L2 cache appears on e500mc and e5500 core. The platform =20 +> +> The backside L2 cache appears on e500mc and e5500 core. The platform > cache > supported by this patch is L2 Look-Aside Cache, which appears on SoCs > with e500v1/e500v2 core, such as MPC8572, P1020, etc. ->=20 +> > Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> > Signed-off-by: Li Yang <leoli@freescale.com> > --- > arch/powerpc/include/asm/cacheflush.h | 8 ++ > arch/powerpc/kernel/Makefile | 1 + -> arch/powerpc/kernel/fsl_booke_cache.S | 210 =20 +> arch/powerpc/kernel/fsl_booke_cache.S | 210 > +++++++++++++++++++++++++++++++++ > arch/powerpc/kernel/head_fsl_booke.S | 74 ------------ > 4 files changed, 219 insertions(+), 74 deletions(-) > create mode 100644 arch/powerpc/kernel/fsl_booke_cache.S ->=20 -> diff --git a/arch/powerpc/include/asm/cacheflush.h =20 +> +> diff --git a/arch/powerpc/include/asm/cacheflush.h > b/arch/powerpc/include/asm/cacheflush.h > index b843e35..bc3f937 100644 > --- a/arch/powerpc/include/asm/cacheflush.h > +++ b/arch/powerpc/include/asm/cacheflush.h > @@ -32,6 +32,14 @@ extern void flush_dcache_page(struct page *page); ->=20 +> > extern void __flush_disable_L1(void); ->=20 +> > +#ifdef CONFIG_FSL_SOC_BOOKE > +void flush_dcache_L1(void); > +void flush_backside_L2_cache(void); @@ -37,16 +37,16 @@ On 04/19/2013 05:47:34 AM, Zhao Chenhui wrote: > +void invalidate_enable_L2(void); > +#endif -Don't ifdef prototypes unless there's a good reason, such as providing =20 +Don't ifdef prototypes unless there's a good reason, such as providing an inline alternative. -Why do you have "flush_backside_L2_cache" and =20 -"disable_backside_L2_cache" as something different from =20 -"flush_disable_L2"? The latter should flush whatever L2 is present. =20 +Why do you have "flush_backside_L2_cache" and +"disable_backside_L2_cache" as something different from +"flush_disable_L2"? The latter should flush whatever L2 is present. Don't treat pre-corenet as the default. -Why do we even need to distinguish L1 from L2 at all? Shouldn't the =20 -function that gets exposed just be "flush and disable data caches that =20 +Why do we even need to distinguish L1 from L2 at all? Shouldn't the +function that gets exposed just be "flush and disable data caches that are specific to this cpu"? What should happen on e6500? --Scott= +-Scott diff --git a/a/content_digest b/N1/content_digest index 0a6b311..547f1fe 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -3,41 +3,41 @@ "Subject\0Re: [PATCH v2 01/15] powerpc/85xx: cache operations for Freescale SoCs based on BOOK3E\0" "Date\0Tue, 23 Apr 2013 18:46:10 -0500\0" "To\0Zhao Chenhui <chenhui.zhao@freescale.com>\0" - "Cc\0linuxppc-dev@lists.ozlabs.org" - " linux-kernel@vger.kernel.org\0" + "Cc\0<linuxppc-dev@lists.ozlabs.org>" + " <linux-kernel@vger.kernel.org>\0" "\00:1\0" "b\0" "On 04/19/2013 05:47:34 AM, Zhao Chenhui wrote:\n" "> These cache operations support Freescale SoCs based on BOOK3E.\n" "> Move L1 cache operations to fsl_booke_cache.S in order to maintain\n" - "> easily. And, add cache operations for backside L2 cache and platform =20\n" + "> easily. And, add cache operations for backside L2 cache and platform \n" "> cache.\n" - ">=20\n" - "> The backside L2 cache appears on e500mc and e5500 core. The platform =20\n" + "> \n" + "> The backside L2 cache appears on e500mc and e5500 core. The platform \n" "> cache\n" "> supported by this patch is L2 Look-Aside Cache, which appears on SoCs\n" "> with e500v1/e500v2 core, such as MPC8572, P1020, etc.\n" - ">=20\n" + "> \n" "> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>\n" "> Signed-off-by: Li Yang <leoli@freescale.com>\n" "> ---\n" "> arch/powerpc/include/asm/cacheflush.h | 8 ++\n" "> arch/powerpc/kernel/Makefile | 1 +\n" - "> arch/powerpc/kernel/fsl_booke_cache.S | 210 =20\n" + "> arch/powerpc/kernel/fsl_booke_cache.S | 210 \n" "> +++++++++++++++++++++++++++++++++\n" "> arch/powerpc/kernel/head_fsl_booke.S | 74 ------------\n" "> 4 files changed, 219 insertions(+), 74 deletions(-)\n" "> create mode 100644 arch/powerpc/kernel/fsl_booke_cache.S\n" - ">=20\n" - "> diff --git a/arch/powerpc/include/asm/cacheflush.h =20\n" + "> \n" + "> diff --git a/arch/powerpc/include/asm/cacheflush.h \n" "> b/arch/powerpc/include/asm/cacheflush.h\n" "> index b843e35..bc3f937 100644\n" "> --- a/arch/powerpc/include/asm/cacheflush.h\n" "> +++ b/arch/powerpc/include/asm/cacheflush.h\n" "> @@ -32,6 +32,14 @@ extern void flush_dcache_page(struct page *page);\n" - ">=20\n" + "> \n" "> extern void __flush_disable_L1(void);\n" - ">=20\n" + "> \n" "> +#ifdef CONFIG_FSL_SOC_BOOKE\n" "> +void flush_dcache_L1(void);\n" "> +void flush_backside_L2_cache(void);\n" @@ -46,18 +46,18 @@ "> +void invalidate_enable_L2(void);\n" "> +#endif\n" "\n" - "Don't ifdef prototypes unless there's a good reason, such as providing =20\n" + "Don't ifdef prototypes unless there's a good reason, such as providing \n" "an inline alternative.\n" "\n" - "Why do you have \"flush_backside_L2_cache\" and =20\n" - "\"disable_backside_L2_cache\" as something different from =20\n" - "\"flush_disable_L2\"? The latter should flush whatever L2 is present. =20\n" + "Why do you have \"flush_backside_L2_cache\" and \n" + "\"disable_backside_L2_cache\" as something different from \n" + "\"flush_disable_L2\"? The latter should flush whatever L2 is present. \n" "Don't treat pre-corenet as the default.\n" "\n" - "Why do we even need to distinguish L1 from L2 at all? Shouldn't the =20\n" - "function that gets exposed just be \"flush and disable data caches that =20\n" + "Why do we even need to distinguish L1 from L2 at all? Shouldn't the \n" + "function that gets exposed just be \"flush and disable data caches that \n" "are specific to this cpu\"? What should happen on e6500?\n" "\n" - -Scott= + -Scott -f739afefd7124097ce66ca7a06a65df5d039a0243ab6d8b11faff2b4a99f70d1 +f1b8fe118b10edd2db106ad0ba3906a90bcdea3479ce51b7b48e64fd17beb55f
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