diff for duplicates of <1366761535.5825.19@snotra> diff --git a/a/1.txt b/N1/1.txt index 2a66794..3f54ea7 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,27 +1,27 @@ On 04/19/2013 05:47:40 AM, Zhao Chenhui wrote: > From: Chen-Hui Zhao <chenhui.zhao@freescale.com> ->=20 -> In the case of SMP, during the time base sync period, all time bases =20 +> +> In the case of SMP, during the time base sync period, all time bases > of > online cores must stop, then start simultaneously. ->=20 -> There is a RCPM (Run Control/Power Management) module in CoreNet =20 +> +> There is a RCPM (Run Control/Power Management) module in CoreNet > based SoCs. > Define a struct ccsr_rcpm to describe the register map. ->=20 +> > This patch supports SoCs based on e500mc/e5500, such as P4080, P5020, > etc. ->=20 +> > Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> > Signed-off-by: Li Yang <leoli@freescale.com> > --- -> arch/powerpc/include/asm/fsl_guts.h | 38 =20 +> arch/powerpc/include/asm/fsl_guts.h | 38 > +++++++++++++++++++++++++++++++++++ -> arch/powerpc/platforms/85xx/smp.c | 32 =20 +> arch/powerpc/platforms/85xx/smp.c | 32 > +++++++++++++++++++++++++++++ > 2 files changed, 70 insertions(+), 0 deletions(-) ->=20 -> diff --git a/arch/powerpc/include/asm/fsl_guts.h =20 +> +> diff --git a/arch/powerpc/include/asm/fsl_guts.h > b/arch/powerpc/include/asm/fsl_guts.h > index 77ced0b..4eac1cf 100644 > --- a/arch/powerpc/include/asm/fsl_guts.h @@ -29,62 +29,62 @@ On 04/19/2013 05:47:40 AM, Zhao Chenhui wrote: > @@ -106,6 +106,44 @@ struct ccsr_guts { > /* Alternate function signal multiplex control */ > #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x)) ->=20 +> > +struct ccsr_rcpm { > + u8 res0000[4]; > + __be32 cdozsr; /* 0x0004 - Core Doze Status Register */ > + u8 res0008[4]; -> + __be32 cdozcr; /* 0x000c - Core Doze Control Register =20 +> + __be32 cdozcr; /* 0x000c - Core Doze Control Register > */ > + u8 res0010[4]; > + __be32 cnapsr; /* 0x0014 - Core Nap Status Register */ > + u8 res0018[4]; > + __be32 cnapcr; /* 0x001c - Core Nap Control Register */ > + u8 res0020[4]; -> + __be32 cdozpsr; /* 0x0024 - Core Doze Previous Status =20 +> + __be32 cdozpsr; /* 0x0024 - Core Doze Previous Status > Register */ > + u8 res0028[4]; -> + __be32 cnappsr; /* 0x002c - Core Nap Previous Status =20 +> + __be32 cnappsr; /* 0x002c - Core Nap Previous Status > Register */ > + u8 res0030[4]; > + __be32 cwaitsr; /* 0x0034 - Core Wait Status Register */ > + u8 res0038[4]; -> + __be32 cwdtdsr; /* 0x003c - Core watchdog detect status =20 +> + __be32 cwdtdsr; /* 0x003c - Core watchdog detect status > register */ -> + __be32 powmgtcsr; /* 0x0040 - Power Mangement Control & =20 +> + __be32 powmgtcsr; /* 0x0040 - Power Mangement Control & > Status Register */ > + u8 res0044[12]; -> + __be32 ippdexpcr; /* 0x0050 - IP Powerdown Exception =20 +> + __be32 ippdexpcr; /* 0x0050 - IP Powerdown Exception > Control Register */ > + u8 res0054[16]; > + __be32 cpmimr; /* 0x0064 - Core PM IRQ Mask Register */ > + u8 res0068[4]; -> + __be32 cpmcimr; /* 0x006c - Core PM Critical IRQ Mask =20 +> + __be32 cpmcimr; /* 0x006c - Core PM Critical IRQ Mask > Register */ > + u8 res0070[4]; -> + __be32 cpmmcmr; /* 0x0074 - Core PM Machine Check Mask =20 +> + __be32 cpmmcmr; /* 0x0074 - Core PM Machine Check Mask > Register */ > + u8 res0078[4]; > + __be32 cpmnmimr; /* 0x007c - Core PM NMI Mask Register */ > + u8 res0080[4]; -> + __be32 ctbenr; /* 0x0084 - Core Time Base Enable =20 +> + __be32 ctbenr; /* 0x0084 - Core Time Base Enable > Register */ > + u8 res0088[4]; -> + __be32 ctbckselr; /* 0x008c - Core Time Base Clock Select =20 +> + __be32 ctbckselr; /* 0x008c - Core Time Base Clock Select > Register */ > + u8 res0090[4]; -> + __be32 ctbhltcr; /* 0x0094 - Core Time Base Halt Control =20 +> + __be32 ctbhltcr; /* 0x0094 - Core Time Base Halt Control > Register */ > + u8 res0098[4]; -> + __be32 cmcpmaskcr; /* 0x00a4 - Core machine check mask =20 +> + __be32 cmcpmaskcr; /* 0x00a4 - Core machine check mask > control register */ > +}; > + > #ifdef CONFIG_PPC_86xx ->=20 -> #define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA =20 +> +> #define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA > controller/channel set to SSI */ -> diff --git a/arch/powerpc/platforms/85xx/smp.c =20 +> diff --git a/arch/powerpc/platforms/85xx/smp.c > b/arch/powerpc/platforms/85xx/smp.c > index 6a17599..6c2fe6b 100644 > --- a/arch/powerpc/platforms/85xx/smp.c @@ -94,7 +94,7 @@ On 04/19/2013 05:47:40 AM, Zhao Chenhui wrote: > static int tb_req; > static int tb_valid; > +static u32 cur_booting_core; ->=20 +> > +#ifdef CONFIG_PPC_E500MC > +/* get a physical mask of online cores and booting core */ > +static inline u32 get_phy_cpu_mask(void) @@ -102,17 +102,17 @@ On 04/19/2013 05:47:40 AM, Zhao Chenhui wrote: > + u32 mask; > + int cpu; > + -> + mask =3D 1 << cur_booting_core; +> + mask = 1 << cur_booting_core; > + for_each_online_cpu(cpu) -> + mask |=3D 1 << get_hard_smp_processor_id(cpu); +> + mask |= 1 << get_hard_smp_processor_id(cpu); > + > + return mask; > +} > + > +static void mpc85xx_timebase_freeze(int freeze) > +{ -> + struct ccsr_rcpm __iomem *rcpm =3D (typeof(rcpm))guts; -> + u32 mask =3D get_phy_cpu_mask(); +> + struct ccsr_rcpm __iomem *rcpm = (typeof(rcpm))guts; +> + u32 mask = get_phy_cpu_mask(); > + > + if (freeze) > + clrbits32(&rcpm->ctbenr, mask); @@ -124,9 +124,9 @@ On 04/19/2013 05:47:40 AM, Zhao Chenhui wrote: > +} > +#else -Please determine the timebase sync implementation at runtime, rather =20 -than relying on our current inability to have e500v2 and e500mc in the =20 -same kernel. e6500 will be different from e5500, but both can be in =20 +Please determine the timebase sync implementation at runtime, rather +than relying on our current inability to have e500v2 and e500mc in the +same kernel. e6500 will be different from e5500, but both can be in the same kernel image. --Scott= +-Scott diff --git a/a/content_digest b/N1/content_digest index 1354545..9646c92 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -4,34 +4,34 @@ "Subject\0Re: [PATCH v2 07/15] powerpc/85xx: add time base sync for SoCs based on e500mc/e5500\0" "Date\0Tue, 23 Apr 2013 18:58:55 -0500\0" "To\0Zhao Chenhui <chenhui.zhao@freescale.com>\0" - "Cc\0linuxppc-dev@lists.ozlabs.org" - " linux-kernel@vger.kernel.org\0" + "Cc\0<linuxppc-dev@lists.ozlabs.org>" + " <linux-kernel@vger.kernel.org>\0" "\00:1\0" "b\0" "On 04/19/2013 05:47:40 AM, Zhao Chenhui wrote:\n" "> From: Chen-Hui Zhao <chenhui.zhao@freescale.com>\n" - ">=20\n" - "> In the case of SMP, during the time base sync period, all time bases =20\n" + "> \n" + "> In the case of SMP, during the time base sync period, all time bases \n" "> of\n" "> online cores must stop, then start simultaneously.\n" - ">=20\n" - "> There is a RCPM (Run Control/Power Management) module in CoreNet =20\n" + "> \n" + "> There is a RCPM (Run Control/Power Management) module in CoreNet \n" "> based SoCs.\n" "> Define a struct ccsr_rcpm to describe the register map.\n" - ">=20\n" + "> \n" "> This patch supports SoCs based on e500mc/e5500, such as P4080, P5020,\n" "> etc.\n" - ">=20\n" + "> \n" "> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>\n" "> Signed-off-by: Li Yang <leoli@freescale.com>\n" "> ---\n" - "> arch/powerpc/include/asm/fsl_guts.h | 38 =20\n" + "> arch/powerpc/include/asm/fsl_guts.h | 38 \n" "> +++++++++++++++++++++++++++++++++++\n" - "> arch/powerpc/platforms/85xx/smp.c | 32 =20\n" + "> arch/powerpc/platforms/85xx/smp.c | 32 \n" "> +++++++++++++++++++++++++++++\n" "> 2 files changed, 70 insertions(+), 0 deletions(-)\n" - ">=20\n" - "> diff --git a/arch/powerpc/include/asm/fsl_guts.h =20\n" + "> \n" + "> diff --git a/arch/powerpc/include/asm/fsl_guts.h \n" "> b/arch/powerpc/include/asm/fsl_guts.h\n" "> index 77ced0b..4eac1cf 100644\n" "> --- a/arch/powerpc/include/asm/fsl_guts.h\n" @@ -39,62 +39,62 @@ "> @@ -106,6 +106,44 @@ struct ccsr_guts {\n" "> /* Alternate function signal multiplex control */\n" "> #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))\n" - ">=20\n" + "> \n" "> +struct ccsr_rcpm {\n" "> +\tu8\tres0000[4];\n" "> +\t__be32\tcdozsr;\t\t/* 0x0004 - Core Doze Status Register */\n" "> +\tu8\tres0008[4];\n" - "> +\t__be32\tcdozcr;\t\t/* 0x000c - Core Doze Control Register =20\n" + "> +\t__be32\tcdozcr;\t\t/* 0x000c - Core Doze Control Register \n" "> */\n" "> +\tu8\tres0010[4];\n" "> +\t__be32\tcnapsr;\t\t/* 0x0014 - Core Nap Status Register */\n" "> +\tu8\tres0018[4];\n" "> +\t__be32\tcnapcr;\t\t/* 0x001c - Core Nap Control Register */\n" "> +\tu8\tres0020[4];\n" - "> +\t__be32\tcdozpsr;\t/* 0x0024 - Core Doze Previous Status =20\n" + "> +\t__be32\tcdozpsr;\t/* 0x0024 - Core Doze Previous Status \n" "> Register */\n" "> +\tu8\tres0028[4];\n" - "> +\t__be32\tcnappsr;\t/* 0x002c - Core Nap Previous Status =20\n" + "> +\t__be32\tcnappsr;\t/* 0x002c - Core Nap Previous Status \n" "> Register */\n" "> +\tu8\tres0030[4];\n" "> +\t__be32\tcwaitsr;\t/* 0x0034 - Core Wait Status Register */\n" "> +\tu8\tres0038[4];\n" - "> +\t__be32\tcwdtdsr;\t/* 0x003c - Core watchdog detect status =20\n" + "> +\t__be32\tcwdtdsr;\t/* 0x003c - Core watchdog detect status \n" "> register */\n" - "> +\t__be32\tpowmgtcsr;\t/* 0x0040 - Power Mangement Control & =20\n" + "> +\t__be32\tpowmgtcsr;\t/* 0x0040 - Power Mangement Control & \n" "> Status Register */\n" "> +\tu8\tres0044[12];\n" - "> +\t__be32\tippdexpcr;\t/* 0x0050 - IP Powerdown Exception =20\n" + "> +\t__be32\tippdexpcr;\t/* 0x0050 - IP Powerdown Exception \n" "> Control Register */\n" "> +\tu8\tres0054[16];\n" "> +\t__be32\tcpmimr;\t\t/* 0x0064 - Core PM IRQ Mask Register */\n" "> +\tu8\tres0068[4];\n" - "> +\t__be32\tcpmcimr;\t/* 0x006c - Core PM Critical IRQ Mask =20\n" + "> +\t__be32\tcpmcimr;\t/* 0x006c - Core PM Critical IRQ Mask \n" "> Register */\n" "> +\tu8\tres0070[4];\n" - "> +\t__be32\tcpmmcmr;\t/* 0x0074 - Core PM Machine Check Mask =20\n" + "> +\t__be32\tcpmmcmr;\t/* 0x0074 - Core PM Machine Check Mask \n" "> Register */\n" "> +\tu8\tres0078[4];\n" "> +\t__be32\tcpmnmimr;\t/* 0x007c - Core PM NMI Mask Register */\n" "> +\tu8\tres0080[4];\n" - "> +\t__be32\tctbenr;\t\t/* 0x0084 - Core Time Base Enable =20\n" + "> +\t__be32\tctbenr;\t\t/* 0x0084 - Core Time Base Enable \n" "> Register */\n" "> +\tu8\tres0088[4];\n" - "> +\t__be32\tctbckselr;\t/* 0x008c - Core Time Base Clock Select =20\n" + "> +\t__be32\tctbckselr;\t/* 0x008c - Core Time Base Clock Select \n" "> Register */\n" "> +\tu8\tres0090[4];\n" - "> +\t__be32\tctbhltcr;\t/* 0x0094 - Core Time Base Halt Control =20\n" + "> +\t__be32\tctbhltcr;\t/* 0x0094 - Core Time Base Halt Control \n" "> Register */\n" "> +\tu8\tres0098[4];\n" - "> +\t__be32\tcmcpmaskcr;\t/* 0x00a4 - Core machine check mask =20\n" + "> +\t__be32\tcmcpmaskcr;\t/* 0x00a4 - Core machine check mask \n" "> control register */\n" "> +};\n" "> +\n" "> #ifdef CONFIG_PPC_86xx\n" - ">=20\n" - "> #define CCSR_GUTS_DMACR_DEV_SSI\t0\t/* DMA =20\n" + "> \n" + "> #define CCSR_GUTS_DMACR_DEV_SSI\t0\t/* DMA \n" "> controller/channel set to SSI */\n" - "> diff --git a/arch/powerpc/platforms/85xx/smp.c =20\n" + "> diff --git a/arch/powerpc/platforms/85xx/smp.c \n" "> b/arch/powerpc/platforms/85xx/smp.c\n" "> index 6a17599..6c2fe6b 100644\n" "> --- a/arch/powerpc/platforms/85xx/smp.c\n" @@ -104,7 +104,7 @@ "> static int tb_req;\n" "> static int tb_valid;\n" "> +static u32 cur_booting_core;\n" - ">=20\n" + "> \n" "> +#ifdef CONFIG_PPC_E500MC\n" "> +/* get a physical mask of online cores and booting core */\n" "> +static inline u32 get_phy_cpu_mask(void)\n" @@ -112,17 +112,17 @@ "> +\tu32 mask;\n" "> +\tint cpu;\n" "> +\n" - "> +\tmask =3D 1 << cur_booting_core;\n" + "> +\tmask = 1 << cur_booting_core;\n" "> +\tfor_each_online_cpu(cpu)\n" - "> +\t\tmask |=3D 1 << get_hard_smp_processor_id(cpu);\n" + "> +\t\tmask |= 1 << get_hard_smp_processor_id(cpu);\n" "> +\n" "> +\treturn mask;\n" "> +}\n" "> +\n" "> +static void mpc85xx_timebase_freeze(int freeze)\n" "> +{\n" - "> +\tstruct ccsr_rcpm __iomem *rcpm =3D (typeof(rcpm))guts;\n" - "> +\tu32 mask =3D get_phy_cpu_mask();\n" + "> +\tstruct ccsr_rcpm __iomem *rcpm = (typeof(rcpm))guts;\n" + "> +\tu32 mask = get_phy_cpu_mask();\n" "> +\n" "> +\tif (freeze)\n" "> +\t\tclrbits32(&rcpm->ctbenr, mask);\n" @@ -134,11 +134,11 @@ "> +}\n" "> +#else\n" "\n" - "Please determine the timebase sync implementation at runtime, rather =20\n" - "than relying on our current inability to have e500v2 and e500mc in the =20\n" - "same kernel. e6500 will be different from e5500, but both can be in =20\n" + "Please determine the timebase sync implementation at runtime, rather \n" + "than relying on our current inability to have e500v2 and e500mc in the \n" + "same kernel. e6500 will be different from e5500, but both can be in \n" "the same kernel image.\n" "\n" - -Scott= + -Scott -b30fb7b971f55c100838a197a4ec98bca55cb9eeffa7b50c1cc880a2b8847a15 +53c3b1f5ddf050d03c2c2894c418274b45396db7a171f18640058535c6d6be8d
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