From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
To: Gavin Shan <shangw@linux.vnet.ibm.com>
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 4/7] powerpc/powernv: Patch MSI EOI handler on P8
Date: Thu, 25 Apr 2013 06:49:40 +1000 [thread overview]
Message-ID: <1366836580.2869.16.camel@pasglop> (raw)
In-Reply-To: <1366796259-29412-5-git-send-email-shangw@linux.vnet.ibm.com>
On Wed, 2013-04-24 at 17:37 +0800, Gavin Shan wrote:
> The EOI handler of MSI/MSI-X interrupts for P8 (PHB3) need additional
> steps to handle the P/Q bits in IVE before EOIing the corresponding
> interrupt. The patch changes the EOI handler to cover that.
.../...
> static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
> {
> unsigned int count;
> @@ -667,6 +681,8 @@ static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
> }
>
> phb->msi_setup = pnv_pci_ioda_msi_setup;
> + if (phb->type == PNV_PHB_IODA2)
> + phb->msi_eoi = pnv_pci_ioda_msi_eoi;
Ouch, another function pointer call in a hot path...
> phb->msi32_support = 1;
> pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
> count, phb->msi_base);
> diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
> index a11b5a6..ea6a93d 100644
> --- a/arch/powerpc/platforms/powernv/pci.c
> +++ b/arch/powerpc/platforms/powernv/pci.c
> @@ -115,6 +115,25 @@ static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
> irq_dispose_mapping(entry->irq);
> }
> }
> +
> +int pnv_pci_msi_eoi(unsigned int hw_irq)
> +{
> + struct pci_controller *hose, *tmp;
> + struct pnv_phb *phb = NULL;
> +
> + list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
> + phb = hose->private_data;
> + if (hw_irq >= phb->msi_base &&
> + hw_irq < phb->msi_base + phb->msi_bmp.irq_count) {
> + if (!phb->msi_eoi)
> + return -EEXIST;
> + return phb->msi_eoi(phb, hw_irq);
> + }
> + }
> +
> + /* For LSI interrupts, we needn't do it */
> + return 0;
> +}
And a list walk ... that's not right.
Also, you do it for all XICS interrupts, including the non-PCI ones, the
LSIs, etc... only to figure out that some might not be MSIs later in
the loop.
Why not instead look at changing the irq_chip for the MSIs ?
IE. When setting up the MSIs for IODA2, use a different irq_chip which
is a copy of the original one with a different ->eoi callback, which
does the original xics eoi and then the OPAL stuff ?
You might even be able to use something like container_of to get back
to the struct phb, no need to iterate them all.
Cheers,
Ben.
next prev parent reply other threads:[~2013-04-24 20:49 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-24 9:37 [PATCH v3 0/7] powerpc/powernv: PHB3 Support Gavin Shan
2013-04-24 9:37 ` [PATCH 1/7] powerpc/powernv: Supports PHB3 Gavin Shan
2013-04-24 9:37 ` [PATCH 2/7] powerpc/powernv: Retrieve IODA2 tables explicitly Gavin Shan
2013-04-24 9:37 ` [PATCH 3/7] powerpc/powernv: Add option CONFIG_POWERNV_MSI Gavin Shan
2013-04-24 9:37 ` [PATCH 4/7] powerpc/powernv: Patch MSI EOI handler on P8 Gavin Shan
2013-04-24 20:49 ` Benjamin Herrenschmidt [this message]
2013-04-25 8:08 ` Gavin Shan
2013-04-25 8:13 ` Gavin Shan
2013-04-25 8:47 ` Benjamin Herrenschmidt
2013-04-25 11:58 ` Gavin Shan
2013-04-24 9:37 ` [PATCH 5/7] powerpc/powernv: TCE invalidation for PHB3 Gavin Shan
2013-04-24 20:52 ` Benjamin Herrenschmidt
2013-04-25 8:39 ` Gavin Shan
2013-04-24 9:37 ` [PATCH 6/7] powerpc/powernv: Build DMA space for PE on PHB3 Gavin Shan
2013-04-24 9:37 ` [PATCH 7/7] powerpc/powernv: Fix invalid IOMMU table Gavin Shan
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