diff for duplicates of <1366934844.30341.16@snotra> diff --git a/a/1.txt b/N1/1.txt index a05aab3..2ff957c 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -5,7 +5,7 @@ On 04/24/2013 07:28:18 PM, Zhao Chenhui wrote: > > >> On 04/19/2013 05:47:45 AM, Zhao Chenhui wrote: > > >> >From: Chen-Hui Zhao <chenhui.zhao@freescale.com> > > >> > -> > >> >For e6500, two threads in one core share one time base. Just =20 +> > >> >For e6500, two threads in one core share one time base. Just > need > > >> >to do time base sync on first thread of one core, and skip it on > > >> >the other thread. @@ -27,26 +27,26 @@ On 04/24/2013 07:28:18 PM, Zhao Chenhui wrote: > > >> > u32 mask; > > >> > int cpu; > > >> > -> > >> >- mask =3D 1 << cur_booting_core; +> > >> >- mask = 1 << cur_booting_core; > > >> >- for_each_online_cpu(cpu) -> > >> >- mask |=3D 1 << get_hard_smp_processor_id(cpu); +> > >> >- mask |= 1 << get_hard_smp_processor_id(cpu); > > >> >+ if (smt_capable()) { -> > >> >+ /* two threads in one core share one time base =20 +> > >> >+ /* two threads in one core share one time base > */ -> > >> >+ mask =3D 1 << =20 +> > >> >+ mask = 1 << > cpu_core_index_of_thread(cur_booting_core); > > >> >+ for_each_online_cpu(cpu) -> > >> >+ mask |=3D 1 << cpu_core_index_of_thread( -> > >> >+ =20 +> > >> >+ mask |= 1 << cpu_core_index_of_thread( +> > >> >+ > get_hard_smp_processor_id(cpu)); > > >> >+ } else { -> > >> >+ mask =3D 1 << cur_booting_core; +> > >> >+ mask = 1 << cur_booting_core; > > >> >+ for_each_online_cpu(cpu) -> > >> >+ mask |=3D 1 << =20 +> > >> >+ mask |= 1 << > get_hard_smp_processor_id(cpu); > > >> >+ } > > >> -> > >> Where is smt_capable defined()? I assume somewhere in the =20 +> > >> Where is smt_capable defined()? I assume somewhere in the > patchset > > >> but it's a pain to search 12 patches... > > >> @@ -60,16 +60,16 @@ On 04/24/2013 07:28:18 PM, Zhao Chenhui wrote: > > claim that feature yet, except in our SDK kernel. That doesn't > > change the topology of CPU numbering. > > ->=20 +> > Then, where can I get the thread information? dts? > Or, wait for upstream of the thread suppport of e6500. -It's an inherent property of e6500 (outside of some virtualization =20 -scenarios, but you wouldn't run this code under a hypervisor) that you =20 -have two threads per core (whether Linux uses them or not). Or you =20 -could read TMCFG0[NTHRD] if you know you're on a chip that has TMRs but =20 -aren't positive it's an e6500, but I wouldn't bother. If we do ever =20 -have such a chip, there are probably other things that will need =20 +It's an inherent property of e6500 (outside of some virtualization +scenarios, but you wouldn't run this code under a hypervisor) that you +have two threads per core (whether Linux uses them or not). Or you +could read TMCFG0[NTHRD] if you know you're on a chip that has TMRs but +aren't positive it's an e6500, but I wouldn't bother. If we do ever +have such a chip, there are probably other things that will need updating. > > >static inline u32 get_phy_cpu_mask(void) @@ -77,9 +77,9 @@ updating. > > > u32 mask; > > > int cpu; > > > -> > > mask =3D 1 << cpu_core_index_of_thread(cur_booting_core); +> > > mask = 1 << cpu_core_index_of_thread(cur_booting_core); > > > for_each_online_cpu(cpu) -> > > mask |=3D 1 << cpu_core_index_of_thread( +> > > mask |= 1 << cpu_core_index_of_thread( > > > get_hard_smp_processor_id(cpu)); > > > > > > return mask; @@ -89,24 +89,24 @@ updating. > > implemented on a core. > > > > -Scott ->=20 -> Let's look into cpu_core_index_of_thread() in =20 +> +> Let's look into cpu_core_index_of_thread() in > arch/powerpc/kernel/smp.c. ->=20 +> > int cpu_core_index_of_thread(int cpu) > { > return cpu >> threads_shift; > } ->=20 +> > If no thread, the threads_shift is equal to 0. It can work with no > thread. -My point is that if threads are disabled, threads_shift will be 0, but =20 +My point is that if threads are disabled, threads_shift will be 0, but e6500 cores will still be numbered 0, 2, 4, etc. -> Perhaps, I should submit this patch after the thread patches for =20 +> Perhaps, I should submit this patch after the thread patches for > e6500. Why? --Scott= +-Scott diff --git a/a/content_digest b/N1/content_digest index 3d38ff9..843195c 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -3,9 +3,9 @@ "Subject\0Re: [PATCH v2 12/15] powerpc/85xx: add time base sync support for e6500\0" "Date\0Thu, 25 Apr 2013 19:07:24 -0500\0" "To\0Zhao Chenhui <chenhui.zhao@freescale.com>\0" - "Cc\0linuxppc-dev@lists.ozlabs.org" - linux-kernel@vger.kernel.org - " r58472@freescale.com\0" + "Cc\0<linuxppc-dev@lists.ozlabs.org>" + <linux-kernel@vger.kernel.org> + " <r58472@freescale.com>\0" "\00:1\0" "b\0" "On 04/24/2013 07:28:18 PM, Zhao Chenhui wrote:\n" @@ -15,7 +15,7 @@ "> > >> On 04/19/2013 05:47:45 AM, Zhao Chenhui wrote:\n" "> > >> >From: Chen-Hui Zhao <chenhui.zhao@freescale.com>\n" "> > >> >\n" - "> > >> >For e6500, two threads in one core share one time base. Just =20\n" + "> > >> >For e6500, two threads in one core share one time base. Just \n" "> need\n" "> > >> >to do time base sync on first thread of one core, and skip it on\n" "> > >> >the other thread.\n" @@ -37,26 +37,26 @@ "> > >> > \tu32 mask;\n" "> > >> > \tint cpu;\n" "> > >> >\n" - "> > >> >-\tmask =3D 1 << cur_booting_core;\n" + "> > >> >-\tmask = 1 << cur_booting_core;\n" "> > >> >-\tfor_each_online_cpu(cpu)\n" - "> > >> >-\t\tmask |=3D 1 << get_hard_smp_processor_id(cpu);\n" + "> > >> >-\t\tmask |= 1 << get_hard_smp_processor_id(cpu);\n" "> > >> >+\tif (smt_capable()) {\n" - "> > >> >+\t\t/* two threads in one core share one time base =20\n" + "> > >> >+\t\t/* two threads in one core share one time base \n" "> */\n" - "> > >> >+\t\tmask =3D 1 << =20\n" + "> > >> >+\t\tmask = 1 << \n" "> cpu_core_index_of_thread(cur_booting_core);\n" "> > >> >+\t\tfor_each_online_cpu(cpu)\n" - "> > >> >+\t\t\tmask |=3D 1 << cpu_core_index_of_thread(\n" - "> > >> >+\t\t\t\t\t=20\n" + "> > >> >+\t\t\tmask |= 1 << cpu_core_index_of_thread(\n" + "> > >> >+\t\t\t\t\t \n" "> get_hard_smp_processor_id(cpu));\n" "> > >> >+\t} else {\n" - "> > >> >+\t\tmask =3D 1 << cur_booting_core;\n" + "> > >> >+\t\tmask = 1 << cur_booting_core;\n" "> > >> >+\t\tfor_each_online_cpu(cpu)\n" - "> > >> >+\t\t\tmask |=3D 1 << =20\n" + "> > >> >+\t\t\tmask |= 1 << \n" "> get_hard_smp_processor_id(cpu);\n" "> > >> >+\t}\n" "> > >>\n" - "> > >> Where is smt_capable defined()? I assume somewhere in the =20\n" + "> > >> Where is smt_capable defined()? I assume somewhere in the \n" "> patchset\n" "> > >> but it's a pain to search 12 patches...\n" "> > >>\n" @@ -70,16 +70,16 @@ "> > claim that feature yet, except in our SDK kernel. That doesn't\n" "> > change the topology of CPU numbering.\n" "> >\n" - ">=20\n" + "> \n" "> Then, where can I get the thread information? dts?\n" "> Or, wait for upstream of the thread suppport of e6500.\n" "\n" - "It's an inherent property of e6500 (outside of some virtualization =20\n" - "scenarios, but you wouldn't run this code under a hypervisor) that you =20\n" - "have two threads per core (whether Linux uses them or not). Or you =20\n" - "could read TMCFG0[NTHRD] if you know you're on a chip that has TMRs but =20\n" - "aren't positive it's an e6500, but I wouldn't bother. If we do ever =20\n" - "have such a chip, there are probably other things that will need =20\n" + "It's an inherent property of e6500 (outside of some virtualization \n" + "scenarios, but you wouldn't run this code under a hypervisor) that you \n" + "have two threads per core (whether Linux uses them or not). Or you \n" + "could read TMCFG0[NTHRD] if you know you're on a chip that has TMRs but \n" + "aren't positive it's an e6500, but I wouldn't bother. If we do ever \n" + "have such a chip, there are probably other things that will need \n" "updating.\n" "\n" "> > >static inline u32 get_phy_cpu_mask(void)\n" @@ -87,9 +87,9 @@ "> > >\tu32 mask;\n" "> > >\tint cpu;\n" "> > >\n" - "> > >\tmask =3D 1 << cpu_core_index_of_thread(cur_booting_core);\n" + "> > >\tmask = 1 << cpu_core_index_of_thread(cur_booting_core);\n" "> > >\tfor_each_online_cpu(cpu)\n" - "> > >\t\tmask |=3D 1 << cpu_core_index_of_thread(\n" + "> > >\t\tmask |= 1 << cpu_core_index_of_thread(\n" "> > >\t\t\t\tget_hard_smp_processor_id(cpu));\n" "> > >\n" "> > >\treturn mask;\n" @@ -99,26 +99,26 @@ "> > implemented on a core.\n" "> >\n" "> > -Scott\n" - ">=20\n" - "> Let's look into cpu_core_index_of_thread() in =20\n" + "> \n" + "> Let's look into cpu_core_index_of_thread() in \n" "> arch/powerpc/kernel/smp.c.\n" - ">=20\n" + "> \n" "> int cpu_core_index_of_thread(int cpu)\n" "> {\n" "> return cpu >> threads_shift;\n" "> }\n" - ">=20\n" + "> \n" "> If no thread, the threads_shift is equal to 0. It can work with no\n" "> thread.\n" "\n" - "My point is that if threads are disabled, threads_shift will be 0, but =20\n" + "My point is that if threads are disabled, threads_shift will be 0, but \n" "e6500 cores will still be numbered 0, 2, 4, etc.\n" "\n" - "> Perhaps, I should submit this patch after the thread patches for =20\n" + "> Perhaps, I should submit this patch after the thread patches for \n" "> e6500.\n" "\n" "Why?\n" "\n" - -Scott= + -Scott -a77f7999128c19b5c68528d1f3d80912c5240e81262aac60147a3d5bbcfeb204 +f293b31bc9038a432cf2e3a2c0d1664ebcb0a673146b42a63e8563bf9c28181e
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