From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH 2/4] drm/i915: merge VLV eDP and DP AUX clock divider calculation Date: Tue, 21 May 2013 13:36:39 +0300 Message-ID: <1369132599.15652.32.camel@intelbox> References: <1368704437-17034-1-git-send-email-imre.deak@intel.com> <1368704437-17034-3-git-send-email-imre.deak@intel.com> <20130521091201.GG12292@phenom.ffwll.local> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 0CCFDE5C52 for ; Tue, 21 May 2013 03:36:43 -0700 (PDT) In-Reply-To: <20130521091201.GG12292@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, 2013-05-21 at 11:12 +0200, Daniel Vetter wrote: > On Thu, May 16, 2013 at 02:40:35PM +0300, Imre Deak wrote: > > On ValleyView for both eDP and DP the AUX input clock is 200MHz, so we > > can calculate for both the clock divider for the 2MHz target rate at the > > same place. Afterwards we can also replace the is_cpu_edp() check with a > > check for port A. > > > > Signed-off-by: Imre Deak > > There's a now-dead IS_VLV case in intel_hrawclk which should be killed > with this patch, too. Shouldn't it still return the correct value if someone calls it in the future? Actually it's also used in intel_dp_init_panel_power_sequencer_registers(). --Imre > -Daniel > > > --- > > drivers/gpu/drm/i915/intel_dp.c | 6 +++--- > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > > index 90ae58a..b99da13 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -317,11 +317,11 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, > > * Note that PCH attached eDP panels should use a 125MHz input > > * clock divider. > > */ > > - if (is_cpu_edp(intel_dp)) { > > + if (IS_VALLEYVIEW(dev)) { > > + aux_clock_divider = 100; > > + } else if (intel_dig_port->port == PORT_A) { > > if (HAS_DDI(dev)) > > aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1; > > - else if (IS_VALLEYVIEW(dev)) > > - aux_clock_divider = 100; > > else if (IS_GEN6(dev) || IS_GEN7(dev)) > > aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ > > else > > -- > > 1.7.10.4 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx >