From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 5/6] drm/i915: initialize the PCH GTC interrupts Date: Wed, 5 Jun 2013 14:21:55 -0300 Message-ID: <1370452916-3406-6-git-send-email-przanoni@gmail.com> References: <1370452916-3406-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-yh0-f48.google.com (mail-yh0-f48.google.com [209.85.213.48]) by gabe.freedesktop.org (Postfix) with ESMTP id 37DA6E63EF for ; Wed, 5 Jun 2013 10:22:30 -0700 (PDT) Received: by mail-yh0-f48.google.com with SMTP id i72so475971yha.35 for ; Wed, 05 Jun 2013 10:22:30 -0700 (PDT) In-Reply-To: <1370452916-3406-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni These regsiters only exist on LPT and we still don't use them. Initialize them for the same reason as we initialize the other interrupts we don't use (SRD, FDI_RX, AUD). Notice that we also have CPU GTC registers, but these registers are disabled when the power well is disabled, so they must be handled differently. Also, they don't affect the code for package C8+ since we need the power well disabled to enter PC8+. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_irq.c | 15 +++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index c21055e..dc2658c 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2498,6 +2498,11 @@ static void ibx_irq_preinstall(struct drm_device *dev) if (HAS_PCH_LPT(dev)) break; } + + if (HAS_PCH_LPT(dev)) { + I915_WRITE(PCH_GTCIMR, 0xffffffff); + POSTING_READ(PCH_GTCIMR); + } } /* drm_dma.h hooks @@ -2657,6 +2662,11 @@ static void ibx_irq_postinstall(struct drm_device *dev) if (HAS_PCH_LPT(dev)) break; } + + if (HAS_PCH_LPT(dev)) { + I915_WRITE(PCH_GTCIMR, 0xffffffff); + I915_WRITE(PCH_GTCIIR, I915_READ(PCH_GTCIIR)); + } } static int ironlake_irq_postinstall(struct drm_device *dev) @@ -2899,6 +2909,11 @@ static void ironlake_irq_uninstall(struct drm_device *dev) if (HAS_PCH_LPT(dev)) break; } + + if (HAS_PCH_LPT(dev)) { + I915_WRITE(PCH_GTCIMR, 0xffffffff); + I915_WRITE(PCH_GTCIIR, I915_READ(PCH_GTCIIR)); + } } static void i8xx_irq_preinstall(struct drm_device * dev) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f996e9f..6a977ce 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3740,6 +3740,9 @@ #define SRDIMR 0x64834 #define SRDIIR 0x64838 +#define PCH_GTCIMR 0xe7054 +#define PCH_GTCIIR 0xe7058 + #define ILK_DISPLAY_CHICKEN2 0x42004 /* Required on all Ironlake and Sandybridge according to the B-Spec. */ #define ILK_ELPIN_409_SELECT (1 << 25) -- 1.8.1.2