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Date: Mon, 17 Jun 2013 19:42:06 -0500
From: Scott Wood <scottwood@freescale.com>
Subject: Re: [PATCH 3/5] powerpc/dts: update MSI bindings doc for MPIC v4.3
To: Scott Wood <scottwood@freescale.com>
In-Reply-To: <1371515287.9073.15@snotra> (from scottwood@freescale.com on
 Mon Jun 17 19:28:07 2013)
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Cc: Minghuan Lian <Minghuan.Lian@freescale.com>, linuxppc-dev@lists.ozlabs.org,
 Zang Roy-R61911 <r61911@freescale.com>,
 Lian Minghuan-b31939 <B31939@freescale.com>
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On 06/17/2013 07:28:07 PM, Scott Wood wrote:
> On 06/17/2013 12:07:41 AM, Lian Minghuan-b31939 wrote:
>>>> +    compatible =3D "fsl,mpic-msi";
>>>> +    reg =3D <0x41600 0x200 0x44140 4>;
>>>=20
>>> Why 0x200?
>>>=20
>> [Minghuan] The offsets of the MSIA registers are from 0x41600 to =20
>> 0x417ff, and the size is 0x200.
>> offset 0x41600-0x4170 are MSIIRA1-7.
>> 0x41720 is MSISRA,
>> 0x41750 is MSIIR.
>> The others are reserved.
>=20
> There is no MSIIRA on fsl,mpic-msi.

Sigh, I was thinking of MSIIR1A -- which of course is distinct from =20
both MSIIRA1 and MSIIRA. :-P

So it's just a bug that pq3-mpic.dtsi has a length of 0x80?

-Scott=