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From: Darren Etheridge <detheridge@ti.com>
To: robdclark@gmail.com, dri-devel@lists.freedesktop.org,
	airlied@linux.ie, detheridge@ti.com
Cc: panto@antoniou-consulting.com
Subject: [PATCH V2 1/7] drm/tilcdc: support pixel widths greater than 1024
Date: Fri, 21 Jun 2013 13:52:22 -0500	[thread overview]
Message-ID: <1371840748-23621-2-git-send-email-detheridge@ti.com> (raw)
In-Reply-To: <1371840748-23621-1-git-send-email-detheridge@ti.com>

TI LCD controller version 2 has an extended eleventh
bit that enables horizontal resolutions greater than
1024 pixels to be specified (upto 2048).  This patch
adds support for setting this bit on LCDC V2.

Signed-off-by: Darren Etheridge <detheridge@ti.com>
---
 drivers/gpu/drm/tilcdc/tilcdc_crtc.c |   15 +++++++++++++++
 drivers/gpu/drm/tilcdc/tilcdc_regs.h |    1 +
 2 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 5dd3c7d..84fdf25 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -310,6 +310,21 @@ static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
 		((vsw & 0x3f) << 10);
 	tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
 
+	/*
+	 * be sure to set Bit 10 for the V2 LCDC controller,
+	 * otherwise limited to 1024 pixels width, stopping
+	 * 1920x1080 being suppoted.
+	 */
+	if (priv->rev == 2) {
+		if ((mode->vdisplay - 1) & 0x400) {
+			tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
+				LCDC_LPP_B10);
+		} else {
+			tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
+				LCDC_LPP_B10);
+		}
+	}
+
 	/* Configure display type: */
 	reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
 		~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_regs.h b/drivers/gpu/drm/tilcdc/tilcdc_regs.h
index 17fd1b4..1bf5e25 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_regs.h
+++ b/drivers/gpu/drm/tilcdc/tilcdc_regs.h
@@ -80,6 +80,7 @@
 #define LCDC_INVERT_PIXEL_CLOCK                  BIT(22)
 #define LCDC_INVERT_HSYNC                        BIT(21)
 #define LCDC_INVERT_VSYNC                        BIT(20)
+#define LCDC_LPP_B10                             BIT(26)
 
 /* LCDC Block */
 #define LCDC_PID_REG                             0x0
-- 
1.7.0.4

  reply	other threads:[~2013-06-21 19:16 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-06-21 18:52 [PATCH V2 0/7] drm/tilcdc: bug fixes, mode selection improvements Darren Etheridge
2013-06-21 18:52 ` Darren Etheridge [this message]
2013-06-21 18:52 ` [PATCH V2 2/7] drm/tilcdc: adding some more devicetree config Darren Etheridge
2013-06-21 18:52 ` [PATCH V2 3/7] drm/tilcdc: fixing off by one errors found on analyzer Darren Etheridge
2013-06-21 18:52 ` [PATCH V2 4/7] drm/tilcdc: adding more guards to prevent selection of invalid modes Darren Etheridge
2013-06-21 18:52 ` [PATCH V2 5/7] drm/tilcdc: whitespace fixes and tidyup Darren Etheridge
2013-06-21 18:52 ` [PATCH V2 6/7] drm/tilcdc fixing i2c/slave initialization race Darren Etheridge
2013-06-21 18:52 ` [PATCH V2 7/7] drm/tilcdc: Clear bits of register we're going to set Darren Etheridge
2013-06-26 15:42 ` [PATCH V2 0/7] drm/tilcdc: bug fixes, mode selection improvements Rob Clark
2013-06-26 15:47   ` Pantelis Antoniou
2013-06-26 17:49   ` Darren Etheridge

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