From mboxrd@z Thu Jan 1 00:00:00 1970 From: alexdeucher@gmail.com Subject: [PATCH 031/165] drm/radeon/dce8: properly handle interlaced timing Date: Wed, 26 Jun 2013 09:21:51 -0400 Message-ID: <1372253045-17042-32-git-send-email-alexdeucher@gmail.com> References: <1372253045-17042-1-git-send-email-alexdeucher@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-qa0-f47.google.com (mail-qa0-f47.google.com [209.85.216.47]) by gabe.freedesktop.org (Postfix) with ESMTP id 8ECFCE633B for ; Wed, 26 Jun 2013 06:24:34 -0700 (PDT) Received: by mail-qa0-f47.google.com with SMTP id i13so1566260qae.13 for ; Wed, 26 Jun 2013 06:24:34 -0700 (PDT) In-Reply-To: <1372253045-17042-1-git-send-email-alexdeucher@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: dri-devel@lists.freedesktop.org Cc: Alex Deucher List-Id: dri-devel@lists.freedesktop.org From: Alex Deucher The register bits changed on DCE8 compared to previous families. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/atombios_encoders.c | 8 +++++++- drivers/gpu/drm/radeon/cik_reg.h | 3 +++ 2 files changed, 10 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c index 4120d35..4439419 100644 --- a/drivers/gpu/drm/radeon/atombios_encoders.c +++ b/drivers/gpu/drm/radeon/atombios_encoders.c @@ -1962,7 +1962,13 @@ atombios_apply_encoder_quirks(struct drm_encoder *encoder, /* set scaler clears this on some chips */ if (ASIC_IS_AVIVO(rdev) && (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { - if (ASIC_IS_DCE4(rdev)) { + if (ASIC_IS_DCE8(rdev)) { + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, + CIK_INTERLEAVE_EN); + else + WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); + } else if (ASIC_IS_DCE4(rdev)) { if (mode->flags & DRM_MODE_FLAG_INTERLACE) WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, EVERGREEN_INTERLEAVE_EN); diff --git a/drivers/gpu/drm/radeon/cik_reg.h b/drivers/gpu/drm/radeon/cik_reg.h index b96dac0..58b29b5 100644 --- a/drivers/gpu/drm/radeon/cik_reg.h +++ b/drivers/gpu/drm/radeon/cik_reg.h @@ -62,4 +62,7 @@ #define CIK_ALPHA_CONTROL 0x6af0 # define CIK_CURSOR_ALPHA_BLND_ENA (1 << 1) +#define CIK_LB_DATA_FORMAT 0x6b00 +# define CIK_INTERLEAVE_EN (1 << 3) + #endif -- 1.7.7.5