From mboxrd@z Thu Jan 1 00:00:00 1970 From: alexdeucher@gmail.com Subject: [PATCH 043/165] drm/radeon: add indirect register accessors for SMC registers Date: Wed, 26 Jun 2013 09:22:03 -0400 Message-ID: <1372253045-17042-44-git-send-email-alexdeucher@gmail.com> References: <1372253045-17042-1-git-send-email-alexdeucher@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-qe0-f52.google.com (mail-qe0-f52.google.com [209.85.128.52]) by gabe.freedesktop.org (Postfix) with ESMTP id B39DBE636A for ; Wed, 26 Jun 2013 06:24:42 -0700 (PDT) Received: by mail-qe0-f52.google.com with SMTP id i11so947399qej.11 for ; Wed, 26 Jun 2013 06:24:42 -0700 (PDT) In-Reply-To: <1372253045-17042-1-git-send-email-alexdeucher@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: dri-devel@lists.freedesktop.org Cc: Alex Deucher List-Id: dri-devel@lists.freedesktop.org From: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/evergreen_reg.h | 4 ++++ drivers/gpu/drm/radeon/radeon.h | 17 +++++++++++++++++ 2 files changed, 21 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h index 881aba2..50948ac 100644 --- a/drivers/gpu/drm/radeon/evergreen_reg.h +++ b/drivers/gpu/drm/radeon/evergreen_reg.h @@ -24,6 +24,10 @@ #ifndef __EVERGREEN_REG_H__ #define __EVERGREEN_REG_H__ +/* trinity */ +#define TN_SMC_IND_INDEX_0 0x200 +#define TN_SMC_IND_DATA_0 0x204 + /* evergreen */ #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324 diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index b329e99..9af0fa6 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1806,6 +1806,8 @@ void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) +#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) +#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) #define WREG32_P(reg, val, mask) \ do { \ uint32_t tmp_ = RREG32(reg); \ @@ -1844,6 +1846,21 @@ static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uin WREG32(RADEON_PCIE_DATA, (v)); } +static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) +{ + u32 r; + + WREG32(TN_SMC_IND_INDEX_0, (reg)); + r = RREG32(TN_SMC_IND_DATA_0); + return r; +} + +static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) +{ + WREG32(TN_SMC_IND_INDEX_0, (reg)); + WREG32(TN_SMC_IND_DATA_0, (v)); +} + void r100_pll_errata_after_index(struct radeon_device *rdev); -- 1.7.7.5