From mboxrd@z Thu Jan 1 00:00:00 1970 From: alexdeucher@gmail.com Subject: [PATCH 044/165] drm/radeon: add get_xclk() callback for CIK Date: Wed, 26 Jun 2013 09:22:04 -0400 Message-ID: <1372253045-17042-45-git-send-email-alexdeucher@gmail.com> References: <1372253045-17042-1-git-send-email-alexdeucher@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-qe0-f54.google.com (mail-qe0-f54.google.com [209.85.128.54]) by gabe.freedesktop.org (Postfix) with ESMTP id D722AE633B for ; Wed, 26 Jun 2013 06:24:43 -0700 (PDT) Received: by mail-qe0-f54.google.com with SMTP id ne12so927354qeb.41 for ; Wed, 26 Jun 2013 06:24:43 -0700 (PDT) In-Reply-To: <1372253045-17042-1-git-send-email-alexdeucher@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: dri-devel@lists.freedesktop.org Cc: Alex Deucher List-Id: dri-devel@lists.freedesktop.org From: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/cik.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/radeon/cikd.h | 7 +++++++ drivers/gpu/drm/radeon/radeon_asic.h | 1 + 3 files changed, 30 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index aaf7bba..0db0ebc 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -78,6 +78,28 @@ extern void si_rlc_fini(struct radeon_device *rdev); extern int si_rlc_init(struct radeon_device *rdev); static void cik_rlc_stop(struct radeon_device *rdev); +/** + * cik_get_xclk - get the xclk + * + * @rdev: radeon_device pointer + * + * Returns the reference clock used by the gfx engine + * (CIK). + */ +u32 cik_get_xclk(struct radeon_device *rdev) +{ + u32 reference_clock = rdev->clock.spll.reference_freq; + + if (rdev->flags & RADEON_IS_IGP) { + if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK) + return reference_clock / 2; + } else { + if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE) + return reference_clock / 4; + } + return reference_clock; +} + #define BONAIRE_IO_MC_REGS_SIZE 36 static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] = diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h index 8afb334..f00e273 100644 --- a/drivers/gpu/drm/radeon/cikd.h +++ b/drivers/gpu/drm/radeon/cikd.h @@ -28,6 +28,13 @@ #define CIK_RB_BITMAP_WIDTH_PER_SH 2 +/* SMC IND registers */ +#define GENERAL_PWRMGT 0xC0200000 +# define GPU_COUNTER_CLK (1 << 15) + +#define CG_CLKPIN_CNTL 0xC05001A0 +# define XTALIN_DIVIDE (1 << 1) + #define VGA_HDP_CONTROL 0x328 #define VGA_MEMORY_DISABLE (1 << 4) diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index 248da72..05f75f7 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -557,5 +557,6 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); * cik */ uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev); +u32 cik_get_xclk(struct radeon_device *rdev); #endif -- 1.7.7.5