From mboxrd@z Thu Jan 1 00:00:00 1970 From: alexdeucher@gmail.com Subject: [PATCH 062/165] drm/radeon/evergreen: add indirect register accessors for CG registers Date: Wed, 26 Jun 2013 09:22:22 -0400 Message-ID: <1372253045-17042-63-git-send-email-alexdeucher@gmail.com> References: <1372253045-17042-1-git-send-email-alexdeucher@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-qa0-f46.google.com (mail-qa0-f46.google.com [209.85.216.46]) by gabe.freedesktop.org (Postfix) with ESMTP id 6441FE634D for ; Wed, 26 Jun 2013 06:24:56 -0700 (PDT) Received: by mail-qa0-f46.google.com with SMTP id ih17so1548820qab.19 for ; Wed, 26 Jun 2013 06:24:56 -0700 (PDT) In-Reply-To: <1372253045-17042-1-git-send-email-alexdeucher@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: dri-devel@lists.freedesktop.org Cc: Alex Deucher List-Id: dri-devel@lists.freedesktop.org From: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/evergreen_reg.h | 3 +++ drivers/gpu/drm/radeon/radeon.h | 17 +++++++++++++++++ 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h index 50948ac..76630c6b 100644 --- a/drivers/gpu/drm/radeon/evergreen_reg.h +++ b/drivers/gpu/drm/radeon/evergreen_reg.h @@ -44,6 +44,9 @@ #define EVERGREEN_AUDIO_PLL1_DIV 0x5b4 #define EVERGREEN_AUDIO_PLL1_UNK 0x5bc +#define EVERGREEN_CG_IND_ADDR 0x8f8 +#define EVERGREEN_CG_IND_DATA 0x8fc + #define EVERGREEN_AUDIO_ENABLE 0x5e78 #define EVERGREEN_AUDIO_VENDOR_ID 0x5ec0 diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 0814aa7..e73c972 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1853,6 +1853,8 @@ void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v); #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) +#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) +#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) #define WREG32_P(reg, val, mask) \ do { \ uint32_t tmp_ = RREG32(reg); \ @@ -1924,6 +1926,21 @@ static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) WREG32(R600_RCU_DATA, (v)); } +static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) +{ + u32 r; + + WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); + r = RREG32(EVERGREEN_CG_IND_DATA); + return r; +} + +static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) +{ + WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); + WREG32(EVERGREEN_CG_IND_DATA, (v)); +} + void r100_pll_errata_after_index(struct radeon_device *rdev); -- 1.7.7.5