diff for duplicates of <1372665061.36667486@f35.mail.ru> diff --git a/a/1.txt b/N1/1.txt index b1a248d..a763264 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,18 +1,32 @@ -PiBUaGlzIGFkZHMgYSBQQ0kgRXhwcmVzcyBwb3J0IGRyaXZlciBmb3IgdGhlIG9uLWNoaXAgUENJ -IEV4cHJlc3MgcG9ydAo+IHByZXNlbnQgb24gdGhlIGkuTVg2IFNvQy4gIEl0IGlzIGJhc2VkIG9u -IHRoZSBQQ0kgRXhwcmVzcyBkcml2ZXIgYXZhaWxhYmxlCj4gaW4gdGhlIEZyZWVzY2FsZSBCU1Au -Cj4gCj4gU2lnbmVkLW9mZi1ieTogU2VhbiBDcm9zcyA8eG9ic0Brb3NhZ2kuY29tPgouLi4KPiAr -KysgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvcGNpL2lteDZxLXBjaWUudHh0 -Cj4gQEAgLTAsMCArMSwyMCBAQAo+ICsqIEZyZWVzY2FsZSBpLk1YNlEgUENJIEV4cHJlc3MgYnJp -ZGdlCj4gKwo+ICtFeGFtcGxlIChpLk1YNlEpCj4gKwlwY2llOiBwY2llQDAxZmZjMDAwIHsKPiAr -CQljb21wYXRpYmxlID0gImZzbCxpbXg2cS1wY2llIjsKPiArCQlyZWcgPSA8MHgwMWZmYzAwMCAw -eDQwMDA+LAo+ICsJCSAgICAgIDwweDAxMDAwMDAwIDB4MTAwMDAwPiwKPiArCQkgICAgICA8MHgw -MTEwMDAwMCAweGUwMDAwMD4sCj4gKwkJICAgICAgPDB4MDFmMDAwMDAgMHhmYzAwMD47Cj4gKwkJ -aW50ZXJydXB0cyA9IDwwIDEyMiAweDA0PjsKPiArCQljbG9ja3MgPSA8JmNsa3MgMTg2PiwgPCZj -bGtzIDE4OT4sIDwmY2xrcyAxOTY+LAo+ICsJCQkgPCZjbGtzIDE5OD4sIDwmY2xrcyAxNDQ+Owo+ -ICsJCWNsb2NrLW5hbWVzID0gInNhdGFfcmVmIiwgInBjaWVfcmVmXzEyNW0iLCAibHZkczFfc2Vs -IiwKPiArCQkJICAgICAgImx2ZHMxIiwgInBjaWVfYXhpIjsKPiArCQlwb3dlci1lbmFibGUgPSA8 -JmdwaW83IDEyIDA+Owo+ICsJCXBjaWUtcmVzZXQgPSA8JmdwaW8zIDI5IDA+OwoKQ2FuIHRoaXMg -YmUgcmVwbGFjZWQgd2l0aCByZWd1bGF0b3IvcmVzZXQgQVBJPwoKPiArCQl3YWtlLXVwID0gPCZn -cGlvMyAyMiAwPjsKPiArCQlkaXNhYmxlLWVuZHBvaW50ID0gPCZncGlvMiAxNiAwPjsKPiArCX07 -CgotLS0K +> This adds a PCI Express port driver for the on-chip PCI Express port +> present on the i.MX6 SoC. It is based on the PCI Express driver available +> in the Freescale BSP. +> +> Signed-off-by: Sean Cross <xobs@kosagi.com> +... +> +++ b/Documentation/devicetree/bindings/pci/imx6q-pcie.txt +> @@ -0,0 +1,20 @@ +> +* Freescale i.MX6Q PCI Express bridge +> + +> +Example (i.MX6Q) +> + pcie: pcie at 01ffc000 { +> + compatible = "fsl,imx6q-pcie"; +> + reg = <0x01ffc000 0x4000>, +> + <0x01000000 0x100000>, +> + <0x01100000 0xe00000>, +> + <0x01f00000 0xfc000>; +> + interrupts = <0 122 0x04>; +> + clocks = <&clks 186>, <&clks 189>, <&clks 196>, +> + <&clks 198>, <&clks 144>; +> + clock-names = "sata_ref", "pcie_ref_125m", "lvds1_sel", +> + "lvds1", "pcie_axi"; +> + power-enable = <&gpio7 12 0>; +> + pcie-reset = <&gpio3 29 0>; + +Can this be replaced with regulator/reset API? + +> + wake-up = <&gpio3 22 0>; +> + disable-endpoint = <&gpio2 16 0>; +> + }; + +--- diff --git a/a/content_digest b/N1/content_digest index ea84e63..687370e 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,31 +1,42 @@ "ref\01372662947-27160-1-git-send-email-xobs@kosagi.com\0" "ref\01372662947-27160-4-git-send-email-xobs@kosagi.com\0" - "From\0Alexander Shiyan <shc_work@mail.ru>\0" + "From\0shc_work@mail.ru (Alexander Shiyan)\0" "Subject\0Re: [PATCH 3/4] PCI: Add driver for i.MX6 PCI Express\0" "Date\0Mon, 01 Jul 2013 11:51:01 +0400\0" - "To\0Sean Cross <xobs@kosagi.com>\0" - "Cc\0devicetree-discuss@lists.ozlabs.org" - linux-pci@vger.kernel.org - " linux-arm-kernel@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" - "PiBUaGlzIGFkZHMgYSBQQ0kgRXhwcmVzcyBwb3J0IGRyaXZlciBmb3IgdGhlIG9uLWNoaXAgUENJ\n" - "IEV4cHJlc3MgcG9ydAo+IHByZXNlbnQgb24gdGhlIGkuTVg2IFNvQy4gIEl0IGlzIGJhc2VkIG9u\n" - "IHRoZSBQQ0kgRXhwcmVzcyBkcml2ZXIgYXZhaWxhYmxlCj4gaW4gdGhlIEZyZWVzY2FsZSBCU1Au\n" - "Cj4gCj4gU2lnbmVkLW9mZi1ieTogU2VhbiBDcm9zcyA8eG9ic0Brb3NhZ2kuY29tPgouLi4KPiAr\n" - "KysgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvcGNpL2lteDZxLXBjaWUudHh0\n" - "Cj4gQEAgLTAsMCArMSwyMCBAQAo+ICsqIEZyZWVzY2FsZSBpLk1YNlEgUENJIEV4cHJlc3MgYnJp\n" - "ZGdlCj4gKwo+ICtFeGFtcGxlIChpLk1YNlEpCj4gKwlwY2llOiBwY2llQDAxZmZjMDAwIHsKPiAr\n" - "CQljb21wYXRpYmxlID0gImZzbCxpbXg2cS1wY2llIjsKPiArCQlyZWcgPSA8MHgwMWZmYzAwMCAw\n" - "eDQwMDA+LAo+ICsJCSAgICAgIDwweDAxMDAwMDAwIDB4MTAwMDAwPiwKPiArCQkgICAgICA8MHgw\n" - "MTEwMDAwMCAweGUwMDAwMD4sCj4gKwkJICAgICAgPDB4MDFmMDAwMDAgMHhmYzAwMD47Cj4gKwkJ\n" - "aW50ZXJydXB0cyA9IDwwIDEyMiAweDA0PjsKPiArCQljbG9ja3MgPSA8JmNsa3MgMTg2PiwgPCZj\n" - "bGtzIDE4OT4sIDwmY2xrcyAxOTY+LAo+ICsJCQkgPCZjbGtzIDE5OD4sIDwmY2xrcyAxNDQ+Owo+\n" - "ICsJCWNsb2NrLW5hbWVzID0gInNhdGFfcmVmIiwgInBjaWVfcmVmXzEyNW0iLCAibHZkczFfc2Vs\n" - "IiwKPiArCQkJICAgICAgImx2ZHMxIiwgInBjaWVfYXhpIjsKPiArCQlwb3dlci1lbmFibGUgPSA8\n" - "JmdwaW83IDEyIDA+Owo+ICsJCXBjaWUtcmVzZXQgPSA8JmdwaW8zIDI5IDA+OwoKQ2FuIHRoaXMg\n" - "YmUgcmVwbGFjZWQgd2l0aCByZWd1bGF0b3IvcmVzZXQgQVBJPwoKPiArCQl3YWtlLXVwID0gPCZn\n" - "cGlvMyAyMiAwPjsKPiArCQlkaXNhYmxlLWVuZHBvaW50ID0gPCZncGlvMiAxNiAwPjsKPiArCX07\n" - CgotLS0K + "> This adds a PCI Express port driver for the on-chip PCI Express port\n" + "> present on the i.MX6 SoC. It is based on the PCI Express driver available\n" + "> in the Freescale BSP.\n" + "> \n" + "> Signed-off-by: Sean Cross <xobs@kosagi.com>\n" + "...\n" + "> +++ b/Documentation/devicetree/bindings/pci/imx6q-pcie.txt\n" + "> @@ -0,0 +1,20 @@\n" + "> +* Freescale i.MX6Q PCI Express bridge\n" + "> +\n" + "> +Example (i.MX6Q)\n" + "> +\tpcie: pcie at 01ffc000 {\n" + "> +\t\tcompatible = \"fsl,imx6q-pcie\";\n" + "> +\t\treg = <0x01ffc000 0x4000>,\n" + "> +\t\t <0x01000000 0x100000>,\n" + "> +\t\t <0x01100000 0xe00000>,\n" + "> +\t\t <0x01f00000 0xfc000>;\n" + "> +\t\tinterrupts = <0 122 0x04>;\n" + "> +\t\tclocks = <&clks 186>, <&clks 189>, <&clks 196>,\n" + "> +\t\t\t <&clks 198>, <&clks 144>;\n" + "> +\t\tclock-names = \"sata_ref\", \"pcie_ref_125m\", \"lvds1_sel\",\n" + "> +\t\t\t \"lvds1\", \"pcie_axi\";\n" + "> +\t\tpower-enable = <&gpio7 12 0>;\n" + "> +\t\tpcie-reset = <&gpio3 29 0>;\n" + "\n" + "Can this be replaced with regulator/reset API?\n" + "\n" + "> +\t\twake-up = <&gpio3 22 0>;\n" + "> +\t\tdisable-endpoint = <&gpio2 16 0>;\n" + "> +\t};\n" + "\n" + --- -e889a83015ac5d82fec494b998c4a84a41c2a0a8b97ca189a768154c3d9840ee +7ba8530e42650179c6497adda03fc1f0a46805d6932260a618ea5b6eab473963
diff --git a/a/1.txt b/N2/1.txt index b1a248d..6216153 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,18 +1,32 @@ -PiBUaGlzIGFkZHMgYSBQQ0kgRXhwcmVzcyBwb3J0IGRyaXZlciBmb3IgdGhlIG9uLWNoaXAgUENJ -IEV4cHJlc3MgcG9ydAo+IHByZXNlbnQgb24gdGhlIGkuTVg2IFNvQy4gIEl0IGlzIGJhc2VkIG9u -IHRoZSBQQ0kgRXhwcmVzcyBkcml2ZXIgYXZhaWxhYmxlCj4gaW4gdGhlIEZyZWVzY2FsZSBCU1Au -Cj4gCj4gU2lnbmVkLW9mZi1ieTogU2VhbiBDcm9zcyA8eG9ic0Brb3NhZ2kuY29tPgouLi4KPiAr -KysgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvcGNpL2lteDZxLXBjaWUudHh0 -Cj4gQEAgLTAsMCArMSwyMCBAQAo+ICsqIEZyZWVzY2FsZSBpLk1YNlEgUENJIEV4cHJlc3MgYnJp -ZGdlCj4gKwo+ICtFeGFtcGxlIChpLk1YNlEpCj4gKwlwY2llOiBwY2llQDAxZmZjMDAwIHsKPiAr -CQljb21wYXRpYmxlID0gImZzbCxpbXg2cS1wY2llIjsKPiArCQlyZWcgPSA8MHgwMWZmYzAwMCAw -eDQwMDA+LAo+ICsJCSAgICAgIDwweDAxMDAwMDAwIDB4MTAwMDAwPiwKPiArCQkgICAgICA8MHgw -MTEwMDAwMCAweGUwMDAwMD4sCj4gKwkJICAgICAgPDB4MDFmMDAwMDAgMHhmYzAwMD47Cj4gKwkJ -aW50ZXJydXB0cyA9IDwwIDEyMiAweDA0PjsKPiArCQljbG9ja3MgPSA8JmNsa3MgMTg2PiwgPCZj -bGtzIDE4OT4sIDwmY2xrcyAxOTY+LAo+ICsJCQkgPCZjbGtzIDE5OD4sIDwmY2xrcyAxNDQ+Owo+ -ICsJCWNsb2NrLW5hbWVzID0gInNhdGFfcmVmIiwgInBjaWVfcmVmXzEyNW0iLCAibHZkczFfc2Vs -IiwKPiArCQkJICAgICAgImx2ZHMxIiwgInBjaWVfYXhpIjsKPiArCQlwb3dlci1lbmFibGUgPSA8 -JmdwaW83IDEyIDA+Owo+ICsJCXBjaWUtcmVzZXQgPSA8JmdwaW8zIDI5IDA+OwoKQ2FuIHRoaXMg -YmUgcmVwbGFjZWQgd2l0aCByZWd1bGF0b3IvcmVzZXQgQVBJPwoKPiArCQl3YWtlLXVwID0gPCZn -cGlvMyAyMiAwPjsKPiArCQlkaXNhYmxlLWVuZHBvaW50ID0gPCZncGlvMiAxNiAwPjsKPiArCX07 -CgotLS0K +> This adds a PCI Express port driver for the on-chip PCI Express port +> present on the i.MX6 SoC. It is based on the PCI Express driver available +> in the Freescale BSP. +> +> Signed-off-by: Sean Cross <xobs@kosagi.com> +... +> +++ b/Documentation/devicetree/bindings/pci/imx6q-pcie.txt +> @@ -0,0 +1,20 @@ +> +* Freescale i.MX6Q PCI Express bridge +> + +> +Example (i.MX6Q) +> + pcie: pcie@01ffc000 { +> + compatible = "fsl,imx6q-pcie"; +> + reg = <0x01ffc000 0x4000>, +> + <0x01000000 0x100000>, +> + <0x01100000 0xe00000>, +> + <0x01f00000 0xfc000>; +> + interrupts = <0 122 0x04>; +> + clocks = <&clks 186>, <&clks 189>, <&clks 196>, +> + <&clks 198>, <&clks 144>; +> + clock-names = "sata_ref", "pcie_ref_125m", "lvds1_sel", +> + "lvds1", "pcie_axi"; +> + power-enable = <&gpio7 12 0>; +> + pcie-reset = <&gpio3 29 0>; + +Can this be replaced with regulator/reset API? + +> + wake-up = <&gpio3 22 0>; +> + disable-endpoint = <&gpio2 16 0>; +> + }; + +--- diff --git a/a/content_digest b/N2/content_digest index ea84e63..15b2269 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -9,23 +9,37 @@ " linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" - "PiBUaGlzIGFkZHMgYSBQQ0kgRXhwcmVzcyBwb3J0IGRyaXZlciBmb3IgdGhlIG9uLWNoaXAgUENJ\n" - "IEV4cHJlc3MgcG9ydAo+IHByZXNlbnQgb24gdGhlIGkuTVg2IFNvQy4gIEl0IGlzIGJhc2VkIG9u\n" - "IHRoZSBQQ0kgRXhwcmVzcyBkcml2ZXIgYXZhaWxhYmxlCj4gaW4gdGhlIEZyZWVzY2FsZSBCU1Au\n" - "Cj4gCj4gU2lnbmVkLW9mZi1ieTogU2VhbiBDcm9zcyA8eG9ic0Brb3NhZ2kuY29tPgouLi4KPiAr\n" - "KysgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvcGNpL2lteDZxLXBjaWUudHh0\n" - "Cj4gQEAgLTAsMCArMSwyMCBAQAo+ICsqIEZyZWVzY2FsZSBpLk1YNlEgUENJIEV4cHJlc3MgYnJp\n" - "ZGdlCj4gKwo+ICtFeGFtcGxlIChpLk1YNlEpCj4gKwlwY2llOiBwY2llQDAxZmZjMDAwIHsKPiAr\n" - "CQljb21wYXRpYmxlID0gImZzbCxpbXg2cS1wY2llIjsKPiArCQlyZWcgPSA8MHgwMWZmYzAwMCAw\n" - "eDQwMDA+LAo+ICsJCSAgICAgIDwweDAxMDAwMDAwIDB4MTAwMDAwPiwKPiArCQkgICAgICA8MHgw\n" - "MTEwMDAwMCAweGUwMDAwMD4sCj4gKwkJICAgICAgPDB4MDFmMDAwMDAgMHhmYzAwMD47Cj4gKwkJ\n" - "aW50ZXJydXB0cyA9IDwwIDEyMiAweDA0PjsKPiArCQljbG9ja3MgPSA8JmNsa3MgMTg2PiwgPCZj\n" - "bGtzIDE4OT4sIDwmY2xrcyAxOTY+LAo+ICsJCQkgPCZjbGtzIDE5OD4sIDwmY2xrcyAxNDQ+Owo+\n" - "ICsJCWNsb2NrLW5hbWVzID0gInNhdGFfcmVmIiwgInBjaWVfcmVmXzEyNW0iLCAibHZkczFfc2Vs\n" - "IiwKPiArCQkJICAgICAgImx2ZHMxIiwgInBjaWVfYXhpIjsKPiArCQlwb3dlci1lbmFibGUgPSA8\n" - "JmdwaW83IDEyIDA+Owo+ICsJCXBjaWUtcmVzZXQgPSA8JmdwaW8zIDI5IDA+OwoKQ2FuIHRoaXMg\n" - "YmUgcmVwbGFjZWQgd2l0aCByZWd1bGF0b3IvcmVzZXQgQVBJPwoKPiArCQl3YWtlLXVwID0gPCZn\n" - "cGlvMyAyMiAwPjsKPiArCQlkaXNhYmxlLWVuZHBvaW50ID0gPCZncGlvMiAxNiAwPjsKPiArCX07\n" - CgotLS0K + "> This adds a PCI Express port driver for the on-chip PCI Express port\n" + "> present on the i.MX6 SoC. It is based on the PCI Express driver available\n" + "> in the Freescale BSP.\n" + "> \n" + "> Signed-off-by: Sean Cross <xobs@kosagi.com>\n" + "...\n" + "> +++ b/Documentation/devicetree/bindings/pci/imx6q-pcie.txt\n" + "> @@ -0,0 +1,20 @@\n" + "> +* Freescale i.MX6Q PCI Express bridge\n" + "> +\n" + "> +Example (i.MX6Q)\n" + "> +\tpcie: pcie@01ffc000 {\n" + "> +\t\tcompatible = \"fsl,imx6q-pcie\";\n" + "> +\t\treg = <0x01ffc000 0x4000>,\n" + "> +\t\t <0x01000000 0x100000>,\n" + "> +\t\t <0x01100000 0xe00000>,\n" + "> +\t\t <0x01f00000 0xfc000>;\n" + "> +\t\tinterrupts = <0 122 0x04>;\n" + "> +\t\tclocks = <&clks 186>, <&clks 189>, <&clks 196>,\n" + "> +\t\t\t <&clks 198>, <&clks 144>;\n" + "> +\t\tclock-names = \"sata_ref\", \"pcie_ref_125m\", \"lvds1_sel\",\n" + "> +\t\t\t \"lvds1\", \"pcie_axi\";\n" + "> +\t\tpower-enable = <&gpio7 12 0>;\n" + "> +\t\tpcie-reset = <&gpio3 29 0>;\n" + "\n" + "Can this be replaced with regulator/reset API?\n" + "\n" + "> +\t\twake-up = <&gpio3 22 0>;\n" + "> +\t\tdisable-endpoint = <&gpio2 16 0>;\n" + "> +\t};\n" + "\n" + --- -e889a83015ac5d82fec494b998c4a84a41c2a0a8b97ca189a768154c3d9840ee +3ccb887ad783b1eb5ef3c26b556b72609c0b91d640dbf4e1a29728fac4138083
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