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Message-ID: <1372948320.4838.6.camel@phoenix>
Subject: irqchip: sirfsoc: Question about SIRFSOC_NUM_IRQS setting
From: Axel Lin <axel.lin@ingics.com>
To: Barry Song <Baohua.Song@csr.com>
Cc: Arnd Bergmann <arnd@arndb.de>, Thomas Gleixner <tglx@linutronix.de>,
        Maxime Ripard <maxime.ripard@free-electrons.com>,
        linux-kernel@vger.kernel.org
Date: Thu, 04 Jul 2013 22:32:00 +0800
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irq_setup_generic_chip() setup max. 32 interrupts starting from gc->irq_base.

sirfsoc_irq_init()
  -> sirfsoc_alloc_gc()
    -> irq_setup_generic_chip()

In sirfsoc_irq_init(), current code calls
sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32); //Note, SIRFSOC_NUM_IRQS is 128

So I'm wondering if SIRFSOC_NUM_IRQS setting is correct or not.

PS. In initial commit 02c981c07bc95ac1e "ARM: CSR: Adding CSR SiRFprimaII board support"
SIRFSOC_INTENAL_IRQ_END is 59.

Regards,
Axel