From: Scott Wood <scottwood@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] Run a standalone application on a core other than 0
Date: Mon, 8 Jul 2013 13:16:49 -0500 [thread overview]
Message-ID: <1373307409.8183.168@snotra> (raw)
In-Reply-To: <CANFGKe9rMkyFgjdsqFZunA+9f6cKRSuxMM0i55+ZT5nH8vBTyg@mail.gmail.com> (from joao.fernandes@ist.utl.pt on Mon Jul 8 12:22:03 2013)
On 07/08/2013 12:22:03 PM, Jo?o Fernandes wrote:
> Thank you Scott. On a somehow related question, when I use "cpu X
> release"
> to run some code on a core other than 0, the changes to memory made
> by cpu
> X are not made visible globally. I believe this is connected with
> WIMGE
> bits - as soon as disable L1 and L2 it works fine - am I correct? If
> so,
> does core 0 have 0x00000000 - 0x3FFFFFFF and 0x40000000 - 0x7FFFFFFF
> TLB
> entries marked as cache coherent, or do I also have to set them for
> it?
You need to set the M bit in all TLB entries that reference memory that
is shared. U-Boot already does this, but perhaps the code you're
running on the secondary CPU does not? Is U-Boot still running on core
0 at that point?
Also be sure you're using the proper memory barriers to ensure that
changes are seen in the right order.
-Scott
next prev parent reply other threads:[~2013-07-08 18:16 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-02 12:02 [U-Boot] Run a standalone application on a core other than 0 João Fernandes
2013-07-02 21:11 ` Scott Wood
2013-07-08 17:22 ` João Fernandes
2013-07-08 18:16 ` Scott Wood [this message]
[not found] <CANFGKe9S1bBbJncFoZGG9wbWk-JL_8AeoxSKyj=GGGyHsiLsCA@mail.gmail.com>
2013-07-08 21:41 ` Scott Wood
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