From mboxrd@z Thu Jan 1 00:00:00 1970 From: Imre Deak Subject: Re: [PATCH] drm/i915: fix lane bandwidth capping for DP 1.2 sinks Date: Tue, 09 Jul 2013 15:47:42 +0300 Message-ID: <1373374062.7984.17.camel@intelbox> References: <1373366437-15517-1-git-send-email-imre.deak@intel.com> Reply-To: imre.deak@intel.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============2041488543==" Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id B366EE6244 for ; Tue, 9 Jul 2013 05:47:44 -0700 (PDT) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: intel-gfx List-Id: intel-gfx@lists.freedesktop.org --===============2041488543== Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; boundary="=-wEJzHX0sBjn4BEK8jjdu" --=-wEJzHX0sBjn4BEK8jjdu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 2013-07-09 at 14:35 +0200, Daniel Vetter wrote: > On Tue, Jul 9, 2013 at 12:40 PM, Imre Deak wrote: > > DP 1.2 compatible displays may report a 5.4Gbps maximum bandwidth which > > the driver will treat as an invalid value and use 1.62Gbps instead. Fix > > this by capping to 2.7Gbps anything beyond the DP 1.1 bandwidth range. > > > > Signed-off-by: Imre Deak > > --- > > drivers/gpu/drm/i915/intel_dp.c | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/int= el_dp.c > > index 11eb697..c6dd61f 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -71,11 +71,16 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp) > > { > > int max_link_bw =3D intel_dp->dpcd[DP_MAX_LINK_RATE]; > > > > + if (max_link_bw > DP_LINK_BW_2_7) > > + return DP_LINK_BW_2_7; > > + > > switch (max_link_bw) { > > case DP_LINK_BW_1_62: > > case DP_LINK_BW_2_7: >=20 > Shouldn't we just add a new case for 5.4 GHz and cap it appropriately. > As is we'll eat any bogus value > BW_2_7 ... I thought that this is more future proof. We would add proper 5.4 support as part of a bigger 1.2 enabling work, having there a similar capping to BW_5_4 for post DP 1.2 sinks. > -Daniel >=20 > > break; > > default: > > + WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\= n", > > + max_link_bw); > > max_link_bw =3D DP_LINK_BW_1_62; > > break; > > } > > -- > > 1.8.1.2 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx >=20 >=20 >=20 > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch --=-wEJzHX0sBjn4BEK8jjdu Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQEcBAABAgAGBQJR3AZuAAoJEORIIAnNuWDF2gwIANpMC2wQ+9Rp90/0QjMPidHa IC3PUl45nCYNWmbt0lo2QKcjYrPOtYUBzPQkU9C+by46T52hTGhWEmmzb44td2M9 m1p5LpXzY76Pk79mnjRqc0r5N0ohfPSU5Bfu80s9oYQb35wc7Gl49PApEcBfFLSy Z+iXB77JeKIWHUjhlAdjN4p7NghNLEHcYQ1qTh/8DaM0s9ZmBn0vTxxiskaA1BTo vqbQ7M4T55Ss0jf8VqQb0K88rW7BOh5uB2qSCdy6ScT8I3IhXPJf8fnixv3p2HxY nnPG3LmfZdjU5GeWJxb8Tjvnbs2Q45Njr6lHTxsOE3e8Fqv8YNunvl1GNJpiIXA= =M0f0 -----END PGP SIGNATURE----- --=-wEJzHX0sBjn4BEK8jjdu-- --===============2041488543== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============2041488543==--