From: Ben Widawsky <benjamin.widawsky@intel.com>
To: Intel GFX <intel-gfx@lists.freedesktop.org>
Cc: Bryan Bell <bryan.j.bell@intel.com>,
Ben Widawsky <ben@bwidawsk.net>,
Ben Widawsky <benjamin.widawsky@intel.com>
Subject: [PATCH 10/14] intel_l3_parity: Hardware info argument
Date: Tue, 17 Sep 2013 21:12:51 -0700 [thread overview]
Message-ID: <1379477575-2164-10-git-send-email-benjamin.widawsky@intel.com> (raw)
In-Reply-To: <1379477575-2164-1-git-send-email-benjamin.widawsky@intel.com>
Add a new command line argument to the tool which will spit out various
parameters for the giving hardware. As a result of this, some new
defines are added to help with the various info.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
tools/intel_l3_parity.c | 24 ++++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/tools/intel_l3_parity.c b/tools/intel_l3_parity.c
index 507a522..28c47eb 100644
--- a/tools/intel_l3_parity.c
+++ b/tools/intel_l3_parity.c
@@ -38,9 +38,19 @@
#include "intel_gpu_tools.h"
#include "drmtest.h"
-#define NUM_BANKS 4
+static unsigned int devid;
+/* L3 size is always a function of banks. The number of banks cannot be
+ * determined by number of slices however */
+#define MAX_BANKS 4
+#define NUM_BANKS \
+ ((devid == PCI_CHIP_IVYBRIDGE_GT1 || devid == PCI_CHIP_IVYBRIDGE_M_GT1) ? 2 : 4)
#define NUM_SUBBANKS 8
+#define BYTES_PER_BANK (128 << 10)
+/* Each row addresses [up to] 4b. This multiplied by the number of subbanks
+ * will give the L3 size per bank.
+ * TODO: Row size is fixed on IVB, and variable on HSW.*/
#define MAX_ROW (1<<12)
+#define L3_SIZE ((MAX_ROW * 4) * NUM_SUBBANKS * NUM_BANKS)
#define NUM_REGS (NUM_BANKS * NUM_SUBBANKS)
struct __attribute__ ((__packed__)) l3_log_register {
@@ -50,7 +60,7 @@ struct __attribute__ ((__packed__)) l3_log_register {
uint32_t row1_enable : 1;
uint32_t rsvd1 : 4;
uint32_t row1 : 11;
-} l3log[NUM_BANKS][NUM_SUBBANKS];
+} l3log[MAX_BANKS][NUM_SUBBANKS];
static void dumpit(void)
{
@@ -118,6 +128,7 @@ static void usage(const char *name)
" -s, --subbank=[subbank] The subbank to act upon (default 0)\n"
" ACTIONS (only 1 may be specified at a time):\n"
" -h, --help Display this help\n"
+ " -H, --hw-info Display the current L3 properties\n"
" -l, --list List the current L3 logs\n"
" -a, --clear-all Clear all disabled rows\n"
" -e, --enable Enable row, bank, subbank (undo -d)\n"
@@ -129,7 +140,6 @@ int main(int argc, char *argv[])
{
const int device = drm_get_card();
char *path;
- unsigned int devid;
int row = 0, bank = 0, sbank = 0;
int drm_fd, fd, ret;
int action = '0';
@@ -162,13 +172,14 @@ int main(int argc, char *argv[])
{ "clear-all", no_argument, 0, 'a' },
{ "enable", no_argument, 0, 'e' },
{ "disable", optional_argument, 0, 'd' },
+ { "hw-info", no_argument, 0, 'H' },
{ "row", required_argument, 0, 'r' },
{ "bank", required_argument, 0, 'b' },
{ "subbank", required_argument, 0, 's' },
{0, 0, 0, 0}
};
- c = getopt_long(argc, argv, "hr:b:s:aled::", long_options,
+ c = getopt_long(argc, argv, "hHr:b:s:aled::", long_options,
&option_index);
if (c == -1)
break;
@@ -178,6 +189,11 @@ int main(int argc, char *argv[])
case 'h':
usage(argv[0]);
exit(EXIT_SUCCESS);
+ case 'H':
+ printf("Number of banks: %d\n", NUM_BANKS);
+ printf("Subbanks per bank: %d\n", NUM_SUBBANKS);
+ printf("L3 size: %dK\n", L3_SIZE >> 10);
+ exit(EXIT_SUCCESS);
case 'r':
row = atoi(optarg);
if (row >= MAX_ROW)
--
1.8.4
next prev parent reply other threads:[~2013-09-18 4:13 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-18 4:12 [PATCH 1/6] drm/i915: Fix HSW parity test Ben Widawsky
2013-09-18 4:12 ` [PATCH 2/6] drm/i915: Add second slice l3 remapping Ben Widawsky
2013-09-18 7:36 ` Ville Syrjälä
2013-09-18 16:22 ` Ben Widawsky
2013-09-19 18:13 ` [PATCH] [v3] " Ben Widawsky
2013-09-18 4:12 ` [PATCH 3/6] drm/i915: Make l3 remapping use the ring Ben Widawsky
2013-09-19 18:39 ` Daniel Vetter
2013-09-18 4:12 ` [PATCH 4/6] drm/i915: Keep a list of all contexts Ben Widawsky
2013-09-18 4:12 ` [PATCH 5/6] drm/i915: Do remaps for " Ben Widawsky
2013-09-18 7:48 ` Ville Syrjälä
2013-09-19 1:14 ` Ben Widawsky
2013-09-19 1:17 ` Ben Widawsky
2013-09-19 2:03 ` [PATCH] [v3] " Ben Widawsky
2013-09-18 4:12 ` [PATCH 6/6] drm/i915: s/HAS_L3_GPU_CACHE/HAS_L3_DPF Ben Widawsky
2013-09-18 7:50 ` Ville Syrjälä
2013-09-19 17:47 ` [PATCH] [v2] " Ben Widawsky
2013-09-19 18:01 ` Ben Widawsky
2013-09-19 18:41 ` Daniel Vetter
2013-09-19 19:59 ` Ben Widawsky
2013-09-18 4:12 ` [PATCH 07/14] intel_l3_parity: Fix indentation Ben Widawsky
2013-09-18 4:12 ` [PATCH 08/14] intel_l3_parity: Assert all GEN7+ support Ben Widawsky
2013-09-18 4:12 ` [PATCH 09/14] intel_l3_parity: Use getopt for the l3 parity tool Ben Widawsky
2013-09-18 4:12 ` Ben Widawsky [this message]
2013-09-18 4:12 ` [PATCH 11/14] intel_l3_parity: slice support Ben Widawsky
2013-09-18 4:12 ` [PATCH 12/14] intel_l3_parity: Actually support multiple slices Ben Widawsky
2013-09-18 4:12 ` [PATCH 13/14] intel_l3_parity: Support error injection Ben Widawsky
2013-09-18 4:12 ` [PATCH 14/14] intel_l3_parity: Support a daemonic mode Ben Widawsky
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