From: Paulo Zanoni <przanoni@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH 1/4] drm/i915: promote FIFO underruns to DRM_ERROR
Date: Thu, 19 Sep 2013 17:00:35 -0300 [thread overview]
Message-ID: <1379620838-1491-2-git-send-email-przanoni@gmail.com> (raw)
In-Reply-To: <1379620838-1491-1-git-send-email-przanoni@gmail.com>
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Linus recently complained about screen corruption when coming out of
DPMS on his Haswell machine, and he also mentioned there were no error
messages on the log. I think I can reproduce this problem, and when it
happens I get a "FIFO underrun" message, but since it's just
DRM_DEBUG_DRIVER it's hard to notice. So promote underruns to error
messages because reports containing "I'm getting a FIFO underrun on
pipe A" are way much better than "I'm getting a screen corruption".
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 44 ++++++++++++++++++++---------------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a42f30b..9ecc9d9 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -263,8 +263,8 @@ static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
if (!was_enabled &&
(I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
- DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
- pipe_name(pipe));
+ DRM_ERROR("uncleared fifo underrun on pipe %c\n",
+ pipe_name(pipe));
}
}
}
@@ -339,8 +339,8 @@ static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
if (!was_enabled &&
(tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
- DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
- transcoder_name(pch_transcoder));
+ DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n",
+ transcoder_name(pch_transcoder));
}
}
}
@@ -1115,8 +1115,8 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
*/
if (pipe_stats[pipe] & 0x8000ffff) {
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
- DRM_DEBUG_DRIVER("pipe %c underrun\n",
- pipe_name(pipe));
+ DRM_ERROR("pipe %c underrun\n",
+ pipe_name(pipe));
I915_WRITE(reg, pipe_stats[pipe]);
}
}
@@ -1206,12 +1206,12 @@ static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
if (pch_iir & SDE_TRANSA_FIFO_UNDER)
if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
false))
- DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
+ DRM_ERROR("PCH transcoder A FIFO underrun\n");
if (pch_iir & SDE_TRANSB_FIFO_UNDER)
if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
false))
- DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
+ DRM_ERROR("PCH transcoder B FIFO underrun\n");
}
static void ivb_err_int_handler(struct drm_device *dev)
@@ -1224,15 +1224,15 @@ static void ivb_err_int_handler(struct drm_device *dev)
if (err_int & ERR_INT_FIFO_UNDERRUN_A)
if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
- DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
+ DRM_ERROR("Pipe A FIFO underrun\n");
if (err_int & ERR_INT_FIFO_UNDERRUN_B)
if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
- DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
+ DRM_ERROR("Pipe B FIFO underrun\n");
if (err_int & ERR_INT_FIFO_UNDERRUN_C)
if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
- DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
+ DRM_ERROR("Pipe C FIFO underrun\n");
I915_WRITE(GEN7_ERR_INT, err_int);
}
@@ -1248,17 +1248,17 @@ static void cpt_serr_int_handler(struct drm_device *dev)
if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
false))
- DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
+ DRM_ERROR("PCH transcoder A FIFO underrun\n");
if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
false))
- DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
+ DRM_ERROR("PCH transcoder B FIFO underrun\n");
if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
false))
- DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
+ DRM_ERROR("PCH transcoder C FIFO underrun\n");
I915_WRITE(SERR_INT, serr_int);
}
@@ -1321,11 +1321,11 @@ static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
- DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
+ DRM_ERROR("Pipe A FIFO underrun\n");
if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
- DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
+ DRM_ERROR("Pipe B FIFO underrun\n");
if (de_iir & DE_PLANEA_FLIP_DONE) {
intel_prepare_page_flip(dev, 0);
@@ -2566,8 +2566,8 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
*/
if (pipe_stats[pipe] & 0x8000ffff) {
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
- DRM_DEBUG_DRIVER("pipe %c underrun\n",
- pipe_name(pipe));
+ DRM_ERROR("pipe %c underrun\n",
+ pipe_name(pipe));
I915_WRITE(reg, pipe_stats[pipe]);
}
}
@@ -2737,8 +2737,8 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
/* Clear the PIPE*STAT regs before the IIR */
if (pipe_stats[pipe] & 0x8000ffff) {
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
- DRM_DEBUG_DRIVER("pipe %c underrun\n",
- pipe_name(pipe));
+ DRM_ERROR("pipe %c underrun\n",
+ pipe_name(pipe));
I915_WRITE(reg, pipe_stats[pipe]);
irq_received = true;
}
@@ -2979,8 +2979,8 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
*/
if (pipe_stats[pipe] & 0x8000ffff) {
if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
- DRM_DEBUG_DRIVER("pipe %c underrun\n",
- pipe_name(pipe));
+ DRM_ERROR("pipe %c underrun\n",
+ pipe_name(pipe));
I915_WRITE(reg, pipe_stats[pipe]);
irq_received = 1;
}
--
1.8.3.1
next prev parent reply other threads:[~2013-09-19 20:00 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-19 20:00 [PATCH 0/4] Haswell modeset fixes Paulo Zanoni
2013-09-19 20:00 ` Paulo Zanoni [this message]
2013-09-19 20:16 ` [PATCH 1/4] drm/i915: promote FIFO underruns to DRM_ERROR Chris Wilson
2013-09-19 20:20 ` Paulo Zanoni
2013-09-19 20:27 ` Chris Wilson
2013-09-20 6:32 ` Ville Syrjälä
2013-09-20 18:38 ` Paulo Zanoni
2013-09-19 20:00 ` [PATCH 2/4] drm/i915: don't disable ERR_INT on the IRQ handler Paulo Zanoni
2013-09-19 20:18 ` Chris Wilson
2013-09-20 8:08 ` Daniel Vetter
2013-09-19 20:00 ` [PATCH 3/4] drm/i915: Disable/enable planes as the first/last thing during modeset on HSW Paulo Zanoni
2013-09-19 20:00 ` [PATCH 4/4] drm/i915: implement the Haswell mode set sequence workaround Paulo Zanoni
2013-09-20 6:29 ` Ville Syrjälä
2013-09-20 19:21 ` Paulo Zanoni
2013-10-01 19:24 ` Daniel Vetter
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