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[89.12.42.254]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5dc18628d00sm7899905a12.27.2025.01.28.14.04.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Jan 2025 14:04:09 -0800 (PST) Date: Tue, 28 Jan 2025 22:04:08 +0000 From: Bernhard Beschow To: Peter Maydell CC: qemu-devel@nongnu.org, Paolo Bonzini , =?ISO-8859-1?Q?Marc-Andr=E9_Lureau?= , Alistair Francis , Jean-Christophe Dubois , qemu-arm@nongnu.org, Andrey Smirnov , "Edgar E. Iglesias" Subject: Re: [PATCH 09/21] hw/arm/fsl-imx8mp: Add PCIe support In-Reply-To: References: <20250120203748.4687-1-shentey@gmail.com> <20250120203748.4687-10-shentey@gmail.com> Message-ID: <137C0579-19AB-4D92-82DC-6CBE2422AD6A@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=shentey@gmail.com; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: Phu2GVrnj583 Am 28=2E Januar 2025 14:33:14 UTC schrieb Peter Maydell : >On Mon, 20 Jan 2025 at 20:38, Bernhard Beschow wrot= e: >> >> Linux checks for the PLLs in the PHY to be locked, so implement a model >> emulating that=2E >> >> Signed-off-by: Bernhard Beschow > >> diff --git a/docs/system/arm/imx8mp-evk=2Erst b/docs/system/arm/imx8mp-= evk=2Erst >> index 1514bc5864=2E=2E8d48580cb4 100644 >> --- a/docs/system/arm/imx8mp-evk=2Erst >> +++ b/docs/system/arm/imx8mp-evk=2Erst >> @@ -14,6 +14,7 @@ The ``imx8mp-evk`` machine implements the following d= evices: >> * Generic Interrupt Controller (GICv3) >> * 4 UARTs >> * 3 USDHC Storage Controllers >> + * 1 Designware PCI Express Controller >> * Secure Non-Volatile Storage (SNVS) including an RTC >> * Clock Tree >> >> @@ -62,3 +63,15 @@ Now that everything is prepared the newly built imag= e can be run in the QEMU >> -dtb imx8mp-evk-patched=2Edtb \ >> -append "root=3D/dev/mmcblk2p2" \ >> -drive file=3Dsdcard=2Eimg,if=3Dsd,bus=3D2,format=3Draw,id=3Dmmc= blk2 >> + >> +Using PCI Devices >> +----------------- >> + >> +The PCI Express controller spawns two PCI buses, of which only one can= be used=2E >> +By default QEMU assigns the wrong bus, so the correct one has to be sp= ecified >> +manually by adding ``bus=3Ddw-pcie``=2E For example, when adding an In= tel e1000 >> +network card, the command line looks like: >> + >> +=2E=2E code-block:: bash >> + >> + $ qemu-system-aarch64 -M imximp-evk =2E=2E=2E -device virtio-net-pci= ,bus=3Ddw-pcie > >Why does this happen? Isn't there some way to make QEMU default to >using the right bus? Otherwise there's likely to be a lot of >user confusion because PCI "doesn't work"=2E=2E=2E Yeah, this is really confusing and I forget about it myself=2E I'd appreci= ate any hints here=2E Best regards, Bernhard > >thanks >-- PMM