From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32807) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeXKb-0005W5-6j for qemu-devel@nongnu.org; Thu, 07 Nov 2013 16:41:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VeXKV-0006Sh-8i for qemu-devel@nongnu.org; Thu, 07 Nov 2013 16:41:37 -0500 Received: from mx1.redhat.com ([209.132.183.28]:23341) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VeXKU-0006R3-Id for qemu-devel@nongnu.org; Thu, 07 Nov 2013 16:41:30 -0500 Message-ID: <1383860314.2527.72.camel@localhost.localdomain> From: Marcel Apfelbaum Date: Thu, 07 Nov 2013 23:38:34 +0200 In-Reply-To: <527C06B5.2020401@redhat.com> References: <1383511723-11228-1-git-send-email-marcel.a@redhat.com> <527C023F.2060506@redhat.com> <1383859470.2527.64.camel@localhost.localdomain> <527C06B5.2020401@redhat.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] exec: fix regression by making system-memory region UINT64_MAX size List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: Peter Maydell , "Michael S. Tsirkin" , Jan Kiszka , "edk2-devel@lists.sourceforge.net" , qemu-devel , Jordan Justen , Anthony Liguori , Laszlo Ersek , afaerber , rth@twiddle.net On Thu, 2013-11-07 at 22:31 +0100, Paolo Bonzini wrote: > Il 07/11/2013 22:24, Marcel Apfelbaum ha scritto: > > Thank you Laszlo for the detailed info! > > I think the problem is right above. Why pci-hole and system.flash collide? > > IMHO we should not play with priorities here, better solve the collision. > > We need to audit all the other boards that support PCI... I'll take a > look tomorrow since you guys are off. Thanks Paolo, Let me just point out what I know (or I think I know): 1. Not all architectures have the behavior: "Address space that is not RAM(and friends) is for sure PCI". Only x86 behaves like this (I think). That means that you cannot have a 64bit wide pci-hole with lower priority that catches all accesses that are not for RAM(and firends). 2. If the above is right, and making pci-hole 64 bit wide is not an option, playing with pci-holes/other-region priorities it would be just wrong, it would be only to "fight" with the locality of the memory region's priority. That being said, I am looking forward for your findings. Thanks! Marcel > > Paolo