From: Rob Herring <robherring2@gmail.com>
To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Cc: Mike Turquette <mturquette@linaro.org>,
Rob Herring <rob.herring@calxeda.com>,
Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>
Subject: [PATCH 1/7] dt-bindings: add Calxeda ECX-3000 clock binding
Date: Wed, 4 Dec 2013 17:35:21 -0600 [thread overview]
Message-ID: <1386200127-23143-2-git-send-email-robherring2@gmail.com> (raw)
In-Reply-To: <1386200127-23143-1-git-send-email-robherring2@gmail.com>
From: Rob Herring <rob.herring@calxeda.com>
Add "calxeda,ecx-3000-pll-clock" compatible property for Calxeda ECX-3000
series PLLs.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
---
Documentation/devicetree/bindings/clock/calxeda.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/calxeda.txt b/Documentation/devicetree/bindings/clock/calxeda.txt
index 0a6ac1b..7ebc89c 100644
--- a/Documentation/devicetree/bindings/clock/calxeda.txt
+++ b/Documentation/devicetree/bindings/clock/calxeda.txt
@@ -6,7 +6,7 @@ This binding uses the common clock binding[1].
Required properties:
- compatible : shall be one of the following:
- "calxeda,hb-pll-clock" - for a PLL clock
+ "calxeda,ecx-3000-pll-clock" or "calxeda,hb-pll-clock" - for a PLL clock
"calxeda,hb-a9periph-clock" - The A9 peripheral clock divided from the
A9 clock.
"calxeda,hb-a9bus-clock" - The A9 bus clock divided from the A9 clock.
--
1.8.3.2
next prev parent reply other threads:[~2013-12-04 23:35 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-04 23:35 [PATCH 0/7] Calxeda arm64 clock updates Rob Herring
2013-12-04 23:35 ` Rob Herring
2013-12-04 23:35 ` Rob Herring [this message]
2013-12-04 23:35 ` [PATCH 2/7] dt-bindings: Add property calxeda,pll-max-hz for Calxeda clocks Rob Herring
2013-12-04 23:35 ` [PATCH 3/7] dt-bindings: Add Calxeda system registers binding Rob Herring
2013-12-04 23:35 ` [PATCH 4/7] clk: highbank: prevent glitching when going into bypass mode Rob Herring
2013-12-04 23:35 ` [PATCH 5/7] clk: highbank: allow for different PLL frequency range Rob Herring
2013-12-04 23:35 ` [PATCH 6/7] clk: highbank: allow enabling by user Rob Herring
2013-12-04 23:35 ` [PATCH 7/7] clk: highbank: add DT match for calxeda,ecx-3000-sregs Rob Herring
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