diff for duplicates of <1386260280.3783.4.camel@linux-builds1> diff --git a/a/1.txt b/N1/1.txt index dadcd2f..860a437 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,5 +1,5 @@ On Thu, 2013-12-05 at 11:47 +0000, Mark Rutland wrote: -> On Wed, Dec 04, 2013 at 10:52:55PM +0000, dinguyen@altera.com wrote: +> On Wed, Dec 04, 2013 at 10:52:55PM +0000, dinguyen at altera.com wrote: > > From: Dinh Nguyen <dinguyen@altera.com> > > > > The SDR timing registers for the SD/MMC IP block for SOCFPGA is located diff --git a/a/content_digest b/N1/content_digest index c686895..e1cb68a 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,26 +1,14 @@ "ref\01386197576-3825-1-git-send-email-dinguyen@altera.com\0" "ref\01386197576-3825-4-git-send-email-dinguyen@altera.com\0" "ref\020131205114740.GM29200@e106331-lin.cambridge.arm.com\0" - "From\0Dinh Nguyen <dinguyen@altera.com>\0" - "Subject\0Re: [PATCHv3 3/4] mmc: dw_mmc-socfpga: Clean up SOCFPGA platform specific funcationality\0" + "From\0dinguyen@altera.com (Dinh Nguyen)\0" + "Subject\0[PATCHv3 3/4] mmc: dw_mmc-socfpga: Clean up SOCFPGA platform specific funcationality\0" "Date\0Thu, 5 Dec 2013 10:18:00 -0600\0" - "To\0Mark Rutland <mark.rutland@arm.com>\0" - "Cc\0dinh.linux@gmail.com <dinh.linux@gmail.com>" - arnd@arndb.de <arnd@arndb.de> - mturquette@linaro.org <mturquette@linaro.org> - rob.herring@calxeda.com <rob.herring@calxeda.com> - Pawel Moll <Pawel.Moll@arm.com> - ian.campbell@citrix.com <ian.campbell@citrix.com> - cjb@laptop.org <cjb@laptop.org> - jh80.chung@samsung.com <jh80.chung@samsung.com> - tgih.jun@samsung.com <tgih.jun@samsung.com> - devicetree@vger.kernel.org <devicetree@vger.kernel.org> - linux-mmc@vger.kernel.org <linux-mmc@vger.kernel.org> - " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Thu, 2013-12-05 at 11:47 +0000, Mark Rutland wrote:\n" - "> On Wed, Dec 04, 2013 at 10:52:55PM +0000, dinguyen@altera.com wrote:\n" + "> On Wed, Dec 04, 2013 at 10:52:55PM +0000, dinguyen at altera.com wrote:\n" "> > From: Dinh Nguyen <dinguyen@altera.com>\n" "> > \n" "> > The SDR timing registers for the SD/MMC IP block for SOCFPGA is located\n" @@ -90,4 +78,4 @@ "> Mark.\n" > -e3f97b04af7449dd5568087f0cf7dc1a9f6c52282688e64265558d6d2c9db843 +1eb8c6e8a8cb8616c17a6953e5689a4313d0bcb8373cd9ac96d99a781c38df83
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