From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47638) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VtJy6-0002uC-AY for qemu-devel@nongnu.org; Wed, 18 Dec 2013 11:27:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VtJxx-00072p-Op for qemu-devel@nongnu.org; Wed, 18 Dec 2013 11:27:30 -0500 Received: from mail-ea0-x231.google.com ([2a00:1450:4013:c01::231]:35703) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VtJxx-00072i-Ih for qemu-devel@nongnu.org; Wed, 18 Dec 2013 11:27:21 -0500 Received: by mail-ea0-f177.google.com with SMTP id n15so3642351ead.22 for ; Wed, 18 Dec 2013 08:27:20 -0800 (PST) Message-ID: <1387384032.2585.7.camel@localhost.localdomain> From: Marcel Apfelbaum Date: Wed, 18 Dec 2013 18:27:12 +0200 In-Reply-To: <20131218152227.GA21186@redhat.com> References: <1386753670-11238-1-git-send-email-ghammer@redhat.com> <52B1AFC3.1050809@redhat.com> <20131218152227.GA21186@redhat.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH] piix: do not reset APIC base address (0x80) on piix4_reset. Reply-To: marcel.a@redhat.com List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: Gal Hammer , Paolo Bonzini , "seabios@seabios.org" , qemu-devel@nongnu.org On Wed, 2013-12-18 at 17:22 +0200, Michael S. Tsirkin wrote: > On Wed, Dec 18, 2013 at 03:22:59PM +0100, Paolo Bonzini wrote: > > Il 11/12/2013 10:21, Gal Hammer ha scritto: > > > Fix a bug that was introduced in commit c046e8c4. QEMU fails to > > > resume from suspend mode (S3). > > > > > > Signed-off-by: Gal Hammer > > > --- > > > hw/acpi/piix4.c | 1 - > > > 1 file changed, 1 deletion(-) > > > > > > diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c > > > index 93849c8..5c736a4 100644 > > > --- a/hw/acpi/piix4.c > > > +++ b/hw/acpi/piix4.c > > > @@ -376,7 +376,6 @@ static void piix4_reset(void *opaque) > > > pci_conf[0x5b] = 0; > > > > > > pci_conf[0x40] = 0x01; /* PM io base read only bit */ > > > - pci_conf[0x80] = 0; > > > > > > if (s->kvm_enabled) { > > > /* Mark SMM as already inited (until KVM supports SMM). */ > > > > Note this is not the APIC base address, that one is 80h on the ISA > > bridge (function 0). You're changing the behavior for 80h on the power > > management function, which is function 3. The register is "PMBA—POWER > > MANAGEMENT BASE ADDRESS" and it is indeed initialized by SeaBIOS in > > piix4_pm_setup (src/fw/pciinit.c). > > > > Michael, perhaps a part of pci_setup (same file) should run on S3 resume? > > > > Paolo > > Seems reasonable: either seabios or guest OS must do it, and > guest does not seem to. I was looking into this today, but it seems that we have a problem. We cannot run pci_setup() in init section: .data.varinit.seabios/src/hw/pci.h.66 is VARVERIFY32INIT but used from ['.text.runtime.seabios/src/resume.c.150', '.text.pci_setup'] Any thoughts how to get around this? Thanks, Marcel >