From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 8/3] drm/i915: WARN in case we're enabling the pipe and it's enabled Date: Fri, 17 Jan 2014 13:51:13 -0200 Message-ID: <1389973873-2005-5-git-send-email-przanoni@gmail.com> References: <1389973873-2005-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-qe0-f51.google.com (mail-qe0-f51.google.com [209.85.128.51]) by gabe.freedesktop.org (Postfix) with ESMTP id E3D84106751 for ; Fri, 17 Jan 2014 07:51:38 -0800 (PST) Received: by mail-qe0-f51.google.com with SMTP id d4so3290416qej.38 for ; Fri, 17 Jan 2014 07:51:38 -0800 (PST) In-Reply-To: <1389973873-2005-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni ... and QUIRK_PIPEA_FORCE is not present. I initially thought that case was impossible and just added a WARN on it, but then I was told this case is possible due to QUIRK_PIPEA_FORCE. So let's add a WARN that serves two purposes: - tell us in case we have done something wrong; - document the only case where we expect this. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9f356f9..e2df886 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1791,8 +1791,11 @@ static void intel_enable_pipe(struct intel_crtc *crtc) reg = PIPECONF(cpu_transcoder); val = I915_READ(reg); - if (val & PIPECONF_ENABLE) + if (val & PIPECONF_ENABLE) { + WARN_ON(!(pipe == PIPE_A && + dev_priv->quirks & QUIRK_PIPEA_FORCE)); return; + } I915_WRITE(reg, val | PIPECONF_ENABLE); POSTING_READ(reg); -- 1.8.4.2