From mboxrd@z Thu Jan  1 00:00:00 1970
From: Dario Faggioli <dario.faggioli@citrix.com>
Subject: Re: [PATCH] credit: Change default timeslice to 5ms
Date: Thu, 6 Mar 2014 13:27:56 +0100
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To: George Dunlap <george.dunlap@eu.citrix.com>
Cc: Marcus Granado <Marcus.Granado@eu.citrix.com>, Keir Fraser <keir@xen.org>, Tim Deegan <tim@xen.org>, xen-devel@lists.xen.org, David Vrabel <david.vrabel@citrix.com>, Jan Beulich <jbeulich@suse.com>
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On gio, 2014-03-06 at 12:04 +0000, George Dunlap wrote:
> On 03/05/2014 05:18 PM, David Vrabel wrote:
> > On 05/03/14 16:29, George Dunlap wrote:
> >> --- a/xen/common/sched_credit.c
> >> +++ b/xen/common/sched_credit.c
> >> @@ -29,9 +29,9 @@
> >>    * Basic constants
> >>    */
> >>   #define CSCHED_DEFAULT_WEIGHT       256
> >> -#define CSCHED_TICKS_PER_TSLICE     3
> >> -/* Default timeslice: 30ms */
> >> -#define CSCHED_DEFAULT_TSLICE_MS    30
> >> +#define CSCHED_TICKS_PER_TSLICE     1
> > The TICKS_PER_TSLICE change doubles the tick rate.  Is this intentional=
?
> >   It's not mentioned in the commit message.
>=20
> Hmm -- actually, I just realized that Marcus' test was done with 3 ticks=
=20
> per timeslice, so "5ms / 1 tick" has *not* been validated. And this is=
=20
> actually important, because the main purpose of the ticks is to give the=
=20
> scheduler an opportunity to switch VMs out of "BOOST" priority and into=
=20
> "UNDER" priority.  Reducing the ticks per timeslice changes that=20
> dynamic, and would need to be tested separately.
>=20
Which is even higher tick frequency, isn't it? Anyway, you're right, we
should go for the tested solution.

> Also, I just discovered a rather pathological case in general that seems=
=20
> to be in the scheduler, so for the time being let me retract this while=
=20
> I figure that out.
>=20
Care to share some more details about this?

Regards,
Dario

--=20
<<This happens because I choose it to happen!>> (Raistlin Majere)
-----------------------------------------------------------------
Dario Faggioli, Ph.D, http://about.me/dario.faggioli
Senior Software Engineer, Citrix Systems R&D Ltd., Cambridge (UK)


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