From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Graf Date: Thu, 24 Apr 2014 13:12:28 +0000 Subject: [PATCH 01/13] KVM: PPC: Book3S PR: Implement LPCR ONE_REG Message-Id: <1398345160-4830-2-git-send-email-agraf@suse.de> List-Id: References: <1398345160-4830-1-git-send-email-agraf@suse.de> In-Reply-To: <1398345160-4830-1-git-send-email-agraf@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: kvm-ppc@vger.kernel.org Cc: kvm@vger.kernel.org, anton@samba.org To control whether we should inject interrupts in little or big endian mode, user space sets the LPCR.ILE bit accordingly via ONE_REG. Let's implement it, so we are able to trigger interrupts in LE mode. Signed-off-by: Alexander Graf --- arch/powerpc/include/asm/kvm_book3s.h | 1 + arch/powerpc/kvm/book3s_64_mmu.c | 8 +++++++- arch/powerpc/kvm/book3s_pr.c | 6 ++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h index bb1e38a..27b1041 100644 --- a/arch/powerpc/include/asm/kvm_book3s.h +++ b/arch/powerpc/include/asm/kvm_book3s.h @@ -106,6 +106,7 @@ struct kvmppc_vcpu_book3s { #endif int hpte_cache_count; spinlock_t mmu_lock; + ulong lpcr; }; #define CONTEXT_HOST 0 diff --git a/arch/powerpc/kvm/book3s_64_mmu.c b/arch/powerpc/kvm/book3s_64_mmu.c index 83da1f8..4a77725 100644 --- a/arch/powerpc/kvm/book3s_64_mmu.c +++ b/arch/powerpc/kvm/book3s_64_mmu.c @@ -38,7 +38,13 @@ static void kvmppc_mmu_book3s_64_reset_msr(struct kvm_vcpu *vcpu) { - kvmppc_set_msr(vcpu, MSR_SF); + struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); + ulong new_msr = MSR_SF; + + if (vcpu_book3s->lpcr & LPCR_ILE) + new_msr |= MSR_LE; + + kvmppc_set_msr(vcpu, new_msr); } static struct kvmppc_slb *kvmppc_mmu_book3s_64_find_slbe( diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index c5c052a..9189ac5 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -1110,6 +1110,9 @@ static int kvmppc_get_one_reg_pr(struct kvm_vcpu *vcpu, u64 id, case KVM_REG_PPC_HIOR: *val = get_reg_val(id, to_book3s(vcpu)->hior); break; + case KVM_REG_PPC_LPCR: + *val = get_reg_val(id, to_book3s(vcpu)->lpcr); + break; default: r = -EINVAL; break; @@ -1128,6 +1131,9 @@ static int kvmppc_set_one_reg_pr(struct kvm_vcpu *vcpu, u64 id, to_book3s(vcpu)->hior = set_reg_val(id, *val); to_book3s(vcpu)->hior_explicit = true; break; + case KVM_REG_PPC_LPCR: + to_book3s(vcpu)->lpcr = set_reg_val(id, *val) & LPCR_ILE; + break; default: r = -EINVAL; break; -- 1.8.1.4 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Graf Subject: [PATCH 01/13] KVM: PPC: Book3S PR: Implement LPCR ONE_REG Date: Thu, 24 Apr 2014 15:12:28 +0200 Message-ID: <1398345160-4830-2-git-send-email-agraf@suse.de> References: <1398345160-4830-1-git-send-email-agraf@suse.de> Cc: kvm@vger.kernel.org, anton@samba.org To: kvm-ppc@vger.kernel.org Return-path: Received: from cantor2.suse.de ([195.135.220.15]:52135 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754234AbaDXNMl (ORCPT ); Thu, 24 Apr 2014 09:12:41 -0400 In-Reply-To: <1398345160-4830-1-git-send-email-agraf@suse.de> Sender: kvm-owner@vger.kernel.org List-ID: To control whether we should inject interrupts in little or big endian mode, user space sets the LPCR.ILE bit accordingly via ONE_REG. Let's implement it, so we are able to trigger interrupts in LE mode. Signed-off-by: Alexander Graf --- arch/powerpc/include/asm/kvm_book3s.h | 1 + arch/powerpc/kvm/book3s_64_mmu.c | 8 +++++++- arch/powerpc/kvm/book3s_pr.c | 6 ++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h index bb1e38a..27b1041 100644 --- a/arch/powerpc/include/asm/kvm_book3s.h +++ b/arch/powerpc/include/asm/kvm_book3s.h @@ -106,6 +106,7 @@ struct kvmppc_vcpu_book3s { #endif int hpte_cache_count; spinlock_t mmu_lock; + ulong lpcr; }; #define CONTEXT_HOST 0 diff --git a/arch/powerpc/kvm/book3s_64_mmu.c b/arch/powerpc/kvm/book3s_64_mmu.c index 83da1f8..4a77725 100644 --- a/arch/powerpc/kvm/book3s_64_mmu.c +++ b/arch/powerpc/kvm/book3s_64_mmu.c @@ -38,7 +38,13 @@ static void kvmppc_mmu_book3s_64_reset_msr(struct kvm_vcpu *vcpu) { - kvmppc_set_msr(vcpu, MSR_SF); + struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu); + ulong new_msr = MSR_SF; + + if (vcpu_book3s->lpcr & LPCR_ILE) + new_msr |= MSR_LE; + + kvmppc_set_msr(vcpu, new_msr); } static struct kvmppc_slb *kvmppc_mmu_book3s_64_find_slbe( diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index c5c052a..9189ac5 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -1110,6 +1110,9 @@ static int kvmppc_get_one_reg_pr(struct kvm_vcpu *vcpu, u64 id, case KVM_REG_PPC_HIOR: *val = get_reg_val(id, to_book3s(vcpu)->hior); break; + case KVM_REG_PPC_LPCR: + *val = get_reg_val(id, to_book3s(vcpu)->lpcr); + break; default: r = -EINVAL; break; @@ -1128,6 +1131,9 @@ static int kvmppc_set_one_reg_pr(struct kvm_vcpu *vcpu, u64 id, to_book3s(vcpu)->hior = set_reg_val(id, *val); to_book3s(vcpu)->hior_explicit = true; break; + case KVM_REG_PPC_LPCR: + to_book3s(vcpu)->lpcr = set_reg_val(id, *val) & LPCR_ILE; + break; default: r = -EINVAL; break; -- 1.8.1.4