From: "Wu, Fei" <fei2.wu@intel.com>
To: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>,
<pbonzini@redhat.com>, <palmer@dabbelt.com>,
<alistair.francis@wdc.com>, <bin.meng@windriver.com>,
<liwei1518@gmail.com>, <dbarboza@ventanamicro.com>,
<zhiwei_liu@linux.alibaba.com>, <qemu-devel@nongnu.org>,
<qemu-riscv@nongnu.org>, <andrei.warkentin@intel.com>,
<shaolin.xie@alibaba-inc.com>, <ved@rivosinc.com>,
<sunilvl@ventanamicro.com>, <haibo1.xu@intel.com>,
<evan.chai@intel.com>, <yin.wang@intel.com>,
<tech-server-platform@lists.riscv.org>,
<tech-server-soc@lists.riscv.org>
Subject: Re: [RFC 0/2] Add RISC-V Server Platform Reference Board
Date: Tue, 12 Mar 2024 16:59:42 +0800 [thread overview]
Message-ID: <13bb6ef3-be61-4b3d-91c5-887bbcbf6e13@intel.com> (raw)
In-Reply-To: <ff1b2b2a-dc8e-4346-92de-bee9c4b4b31f@linaro.org>
On 3/8/2024 6:15 AM, Marcin Juszkiewicz wrote:
> W dniu 4.03.2024 o 11:25, Fei Wu pisze:
>
>> The RISC-V Server Platform specification[1] defines a standardized
>> set of hardware and software capabilities, that portable system
>> software, such as OS and hypervisors can rely on being present in a
>> RISC-V server platform. This patchset provides a RISC-V Server
>> Platform (RVSP) reference implementation on qemu which is in
>> compliance with the spec as faithful as possible.
>
> I am working on sbsa-ref which is AArch64 Standard Server Platform
> implementation. Will not go through details of rvsp-ref but give some
> potential hints from my work with our platform.
>
Hi Marcin,
Thank you for sharing this.
>
> 1. Consider versioning the platform.
>
> We have 'platform_version'.'major/minor' exported in
> DeviceTree-formatted data. This allows for firmware to know which of
> non-discoverable hardware features exists and which not. We use it to
> disable XHCI controller on older platform version.
>
Looks good, I will add it.
>
> 2. If specification allows to have non-discoverable devices then add some.
>
> This will require you to handle them in firmware in some way. Sooner or
> later some physical hardware will be in same situation so they can use
> your firmware code as reference. We have AHCI and XHCI on system bus
> (hardcoded in firmware).
>
This RFC currently adds the devices like AHCI as PCI devices.
>
> 3. You are going to use EDK2 with ACPI. Hide DT from code there with
> some hardware information library.
>
> For sbsa-ref we created SbsaHardwareInfoLib in
> https://openfw.io/edk2-devel/20240306-no-dt-for-cpu-v6-0-acd8727a1b59@linaro.org/ patchset.
>
Looks good, I will ask my colleague working on FW part to take a look.
Thanks,
Fei.
prev parent reply other threads:[~2024-03-12 9:00 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-04 10:25 [RFC 0/2] Add RISC-V Server Platform Reference Board Fei Wu
2024-03-04 10:25 ` [RFC 1/2] hw/riscv: Add server platform reference machine Fei Wu
2024-03-04 19:35 ` Daniel Henrique Barboza
2024-03-05 5:56 ` Wu, Fei
2024-03-05 9:15 ` Daniel Henrique Barboza
2024-03-06 0:19 ` Alistair Francis
2024-03-06 12:55 ` Wu, Fei
2024-03-06 19:13 ` Atish Kumar Patra
2024-03-07 0:48 ` Alistair Francis
2024-03-07 6:26 ` Wu, Fei
2024-03-08 9:20 ` Andrew Jones
2024-03-11 11:55 ` [RISC-V][tech-server-platform] " Wu, Fei
2024-03-11 14:38 ` [RISC-V][tech-server-soc] " Andrew Jones
2024-03-12 0:19 ` Atish Kumar Patra
2024-03-06 0:27 ` Conor Dooley
2024-03-06 2:41 ` Wu, Fei
2024-03-04 10:25 ` [RFC 2/2] target/riscv: Add server platform reference cpu Fei Wu
2024-03-04 19:43 ` Daniel Henrique Barboza
2024-03-05 5:58 ` [RISC-V][tech-server-soc] " Wu, Fei
2024-03-06 13:26 ` Wu, Fei
2024-03-07 7:36 ` Wu, Fei
2024-03-07 12:17 ` [RISC-V][tech-server-platform] " Heinrich Schuchardt
2024-03-07 19:27 ` Daniel Henrique Barboza
2024-03-07 19:15 ` Daniel Henrique Barboza
2024-03-12 12:33 ` Wu, Fei
2024-03-12 12:52 ` Daniel Henrique Barboza
2024-03-04 11:02 ` [RISC-V][tech-server-platform] [RFC 0/2] Add RISC-V Server Platform Reference Board Heinrich Schuchardt
2024-03-04 11:42 ` Chai, Evan
2024-03-07 22:15 ` Marcin Juszkiewicz
2024-03-12 8:59 ` Wu, Fei [this message]
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