diff for duplicates of <1400620176-7239-10-git-send-email-robherring2@gmail.com> diff --git a/a/1.txt b/N1/1.txt index 2de4431..1f057d1 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,11 +1,11 @@ -From: Rob Herring <robh@kernel.org> +From: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> The versatile dts is missing any clock data. Add the clocks. It is not clear from the documentation where pclk comes from, so for now it is a dummy clock which is sufficient for things to work. -Signed-off-by: Rob Herring <robh@kernel.org> +Signed-off-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> --- arch/arm/boot/dts/versatile-ab.dts | 74 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/versatile-pb.dts | 10 ++++++ @@ -19,25 +19,25 @@ index e4cba63..37e01b4 100644 reg = <0x0 0x08000000>; }; -+ core-module at 10000000 { ++ core-module@10000000 { + compatible = "arm,core-module-versatile"; + reg = <0x10000000 0x200>; + -+ osc24M: oscillator at 24M { ++ osc24M: oscillator@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + /* OSC1 on AB, OSC4 on PB */ -+ osc1: cm_aux_osc at 24M { ++ osc1: cm_aux_osc@24M { + #clock-cells = <0>; + compatible = "arm,versatile-cm-auxosc"; + clocks = <&osc24M>; + }; + + /* The timer clock is the 24 MHz oscillator divided to 1MHz */ -+ timclk: timclk at 1M { ++ timclk: timclk@1M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <24>; @@ -46,14 +46,14 @@ index e4cba63..37e01b4 100644 + }; + + /* Actually hclk ? */ -+ pclk: pclk at 0 { ++ pclk: pclk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + }; + - flash at 34000000 { + flash@34000000 { compatible = "arm,versatile-flash"; reg = <0x34000000 0x4000000>; @@ -79,63 +113,85 @@ @@ -64,7 +64,7 @@ index e4cba63..37e01b4 100644 + clock-names = "apb_pclk"; }; - uart0: uart at 101f1000 { + uart0: uart@101f1000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x101f1000 0x1000>; interrupts = <12>; @@ -72,7 +72,7 @@ index e4cba63..37e01b4 100644 + clock-names = "uartclk", "apb_pclk"; }; - uart1: uart at 101f2000 { + uart1: uart@101f2000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x101f2000 0x1000>; interrupts = <13>; @@ -80,7 +80,7 @@ index e4cba63..37e01b4 100644 + clock-names = "uartclk", "apb_pclk"; }; - uart2: uart at 101f3000 { + uart2: uart@101f3000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x101f3000 0x1000>; interrupts = <14>; @@ -88,21 +88,21 @@ index e4cba63..37e01b4 100644 + clock-names = "uartclk", "apb_pclk"; }; - smc at 10100000 { + smc@10100000 { compatible = "arm,primecell"; reg = <0x10100000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; - mpmc at 10110000 { + mpmc@10110000 { compatible = "arm,primecell"; reg = <0x10110000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; - display at 10120000 { + display@10120000 { compatible = "arm,pl110", "arm,primecell"; reg = <0x10120000 0x1000>; interrupts = <16>; @@ -110,14 +110,14 @@ index e4cba63..37e01b4 100644 + clock-names = "clcd", "apb_pclk"; }; - sctl at 101e0000 { + sctl@101e0000 { compatible = "arm,primecell"; reg = <0x101e0000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; }; - watchdog at 101e1000 { + watchdog@101e1000 { compatible = "arm,primecell"; reg = <0x101e1000 0x1000>; interrupts = <0>; @@ -125,7 +125,7 @@ index e4cba63..37e01b4 100644 + clock-names = "apb_pclk"; }; - timer at 101e2000 { + timer@101e2000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x101e2000 0x1000>; interrupts = <4>; @@ -133,7 +133,7 @@ index e4cba63..37e01b4 100644 + clock-names = "tmrclk", "apb_pclk"; }; - timer at 101e3000 { + timer@101e3000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x101e3000 0x1000>; interrupts = <5>; @@ -141,7 +141,7 @@ index e4cba63..37e01b4 100644 + clock-names = "tmrclk", "apb_pclk"; }; - gpio0: gpio at 101e4000 { + gpio0: gpio@101e4000 { @@ -146,6 +202,8 @@ #gpio-cells = <2>; interrupt-controller; @@ -150,7 +150,7 @@ index e4cba63..37e01b4 100644 + clock-names = "apb_pclk"; }; - gpio1: gpio at 101e5000 { + gpio1: gpio@101e5000 { @@ -156,24 +214,32 @@ #gpio-cells = <2>; interrupt-controller; @@ -159,7 +159,7 @@ index e4cba63..37e01b4 100644 + clock-names = "apb_pclk"; }; - rtc at 101e8000 { + rtc@101e8000 { compatible = "arm,pl030", "arm,primecell"; reg = <0x101e8000 0x1000>; interrupts = <10>; @@ -167,7 +167,7 @@ index e4cba63..37e01b4 100644 + clock-names = "apb_pclk"; }; - sci at 101f0000 { + sci@101f0000 { compatible = "arm,primecell"; reg = <0x101f0000 0x1000>; interrupts = <15>; @@ -175,7 +175,7 @@ index e4cba63..37e01b4 100644 + clock-names = "apb_pclk"; }; - ssp at 101f4000 { + ssp@101f4000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x101f4000 0x1000>; interrupts = <11>; @@ -191,14 +191,14 @@ index e4cba63..37e01b4 100644 + clocks = <&pclk>; + clock-names = "apb_pclk"; }; - mmc at 5000 { + mmc@5000 { compatible = "arm,pl180", "arm,primecell"; reg = < 0x5000 0x1000>; interrupts-extended = <&vic 22 &sic 2>; + clocks = <&osc24M>, <&pclk>; + clock-names = "mclk", "apb_pclk"; }; - kmi at 6000 { + kmi@6000 { compatible = "arm,pl050", "arm,primecell"; reg = <0x6000 0x1000>; interrupt-parent = <&sic>; @@ -206,7 +206,7 @@ index e4cba63..37e01b4 100644 + clocks = <&osc24M>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; }; - kmi at 7000 { + kmi@7000 { compatible = "arm,pl050", "arm,primecell"; reg = <0x7000 0x1000>; interrupt-parent = <&sic>; @@ -228,7 +228,7 @@ index a428541..473081d 100644 + clock-names = "apb_pclk"; }; - gpio3: gpio at 101e7000 { + gpio3: gpio@101e7000 { @@ -23,6 +25,8 @@ #gpio-cells = <2>; interrupt-controller; @@ -245,7 +245,7 @@ index a428541..473081d 100644 + clocks = <&osc24M>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; }; - sci at a000 { + sci@a000 { compatible = "arm,primecell"; reg = <0xa000 0x1000>; interrupt-parent = <&sic>; @@ -253,7 +253,7 @@ index a428541..473081d 100644 + clocks = <&osc24M>; + clock-names = "apb_pclk"; }; - mmc at b000 { + mmc@b000 { compatible = "arm,pl180", "arm,primecell"; reg = <0xb000 0x1000>; interrupts-extended = <&vic 23 &sic 2>; @@ -264,3 +264,8 @@ index a428541..473081d 100644 }; -- 1.9.1 + +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index a40a4ae..b9729ef 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,18 +1,23 @@ "ref\01400620176-7239-1-git-send-email-robherring2@gmail.com\0" - "From\0robherring2@gmail.com (Rob Herring)\0" + "ref\01400620176-7239-1-git-send-email-robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" + "From\0Rob Herring <robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" "Subject\0[PATCH 09/10] dts: versatile: add clock tree\0" "Date\0Tue, 20 May 2014 16:09:35 -0500\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" + " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "Cc\0linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org" + arm-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + " Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>\0" "\00:1\0" "b\0" - "From: Rob Herring <robh@kernel.org>\n" + "From: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>\n" "\n" "The versatile dts is missing any clock data. Add the clocks.\n" "\n" "It is not clear from the documentation where pclk comes from, so for\n" "now it is a dummy clock which is sufficient for things to work.\n" "\n" - "Signed-off-by: Rob Herring <robh@kernel.org>\n" + "Signed-off-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>\n" "---\n" " arch/arm/boot/dts/versatile-ab.dts | 74 ++++++++++++++++++++++++++++++++++++++\n" " arch/arm/boot/dts/versatile-pb.dts | 10 ++++++\n" @@ -26,25 +31,25 @@ " \t\treg = <0x0 0x08000000>;\n" " \t};\n" " \n" - "+\tcore-module at 10000000 {\n" + "+\tcore-module@10000000 {\n" "+\t\tcompatible = \"arm,core-module-versatile\";\n" "+\t\treg = <0x10000000 0x200>;\n" "+\n" - "+\t\tosc24M: oscillator at 24M {\n" + "+\t\tosc24M: oscillator@24M {\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t\tcompatible = \"fixed-clock\";\n" "+\t\t\tclock-frequency = <24000000>;\n" "+\t\t};\n" "+\n" "+\t\t/* OSC1 on AB, OSC4 on PB */\n" - "+\t\tosc1: cm_aux_osc at 24M {\n" + "+\t\tosc1: cm_aux_osc@24M {\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t\tcompatible = \"arm,versatile-cm-auxosc\";\n" "+\t\t\tclocks = <&osc24M>;\n" "+\t\t};\n" "+\n" "+\t\t/* The timer clock is the 24 MHz oscillator divided to 1MHz */\n" - "+\t\ttimclk: timclk at 1M {\n" + "+\t\ttimclk: timclk@1M {\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t\tcompatible = \"fixed-factor-clock\";\n" "+\t\t\tclock-div = <24>;\n" @@ -53,14 +58,14 @@ "+\t\t};\n" "+\n" "+\t\t/* Actually hclk ? */\n" - "+\t\tpclk: pclk at 0 {\n" + "+\t\tpclk: pclk@0 {\n" "+\t\t\t#clock-cells = <0>;\n" "+\t\t\tcompatible = \"fixed-clock\";\n" "+\t\t\tclock-frequency = <0>;\n" "+\t\t};\n" "+\t};\n" "+\n" - " \tflash at 34000000 {\n" + " \tflash@34000000 {\n" " \t\tcompatible = \"arm,versatile-flash\";\n" " \t\treg = <0x34000000 0x4000000>;\n" "@@ -79,63 +113,85 @@\n" @@ -71,7 +76,7 @@ "+\t\t\tclock-names = \"apb_pclk\";\n" " \t\t};\n" " \n" - " \t\tuart0: uart at 101f1000 {\n" + " \t\tuart0: uart@101f1000 {\n" " \t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" " \t\t\treg = <0x101f1000 0x1000>;\n" " \t\t\tinterrupts = <12>;\n" @@ -79,7 +84,7 @@ "+\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" " \t\t};\n" " \n" - " \t\tuart1: uart at 101f2000 {\n" + " \t\tuart1: uart@101f2000 {\n" " \t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" " \t\t\treg = <0x101f2000 0x1000>;\n" " \t\t\tinterrupts = <13>;\n" @@ -87,7 +92,7 @@ "+\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" " \t\t};\n" " \n" - " \t\tuart2: uart at 101f3000 {\n" + " \t\tuart2: uart@101f3000 {\n" " \t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" " \t\t\treg = <0x101f3000 0x1000>;\n" " \t\t\tinterrupts = <14>;\n" @@ -95,21 +100,21 @@ "+\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" " \t\t};\n" " \n" - " \t\tsmc at 10100000 {\n" + " \t\tsmc@10100000 {\n" " \t\t\tcompatible = \"arm,primecell\";\n" " \t\t\treg = <0x10100000 0x1000>;\n" "+\t\t\tclocks = <&pclk>;\n" "+\t\t\tclock-names = \"apb_pclk\";\n" " \t\t};\n" " \n" - " \t\tmpmc at 10110000 {\n" + " \t\tmpmc@10110000 {\n" " \t\t\tcompatible = \"arm,primecell\";\n" " \t\t\treg = <0x10110000 0x1000>;\n" "+\t\t\tclocks = <&pclk>;\n" "+\t\t\tclock-names = \"apb_pclk\";\n" " \t\t};\n" " \n" - " \t\tdisplay at 10120000 {\n" + " \t\tdisplay@10120000 {\n" " \t\t\tcompatible = \"arm,pl110\", \"arm,primecell\";\n" " \t\t\treg = <0x10120000 0x1000>;\n" " \t\t\tinterrupts = <16>;\n" @@ -117,14 +122,14 @@ "+\t\t\tclock-names = \"clcd\", \"apb_pclk\";\n" " \t\t};\n" " \n" - " \t\tsctl at 101e0000 {\n" + " \t\tsctl@101e0000 {\n" " \t\t\tcompatible = \"arm,primecell\";\n" " \t\t\treg = <0x101e0000 0x1000>;\n" "+\t\t\tclocks = <&pclk>;\n" "+\t\t\tclock-names = \"apb_pclk\";\n" " \t\t};\n" " \n" - " \t\twatchdog at 101e1000 {\n" + " \t\twatchdog@101e1000 {\n" " \t\t\tcompatible = \"arm,primecell\";\n" " \t\t\treg = <0x101e1000 0x1000>;\n" " \t\t\tinterrupts = <0>;\n" @@ -132,7 +137,7 @@ "+\t\t\tclock-names = \"apb_pclk\";\n" " \t\t};\n" " \n" - " \t\ttimer at 101e2000 {\n" + " \t\ttimer@101e2000 {\n" " \t\t\tcompatible = \"arm,sp804\", \"arm,primecell\";\n" " \t\t\treg = <0x101e2000 0x1000>;\n" " \t\t\tinterrupts = <4>;\n" @@ -140,7 +145,7 @@ "+\t\t\tclock-names = \"tmrclk\", \"apb_pclk\";\n" " \t\t};\n" " \n" - " \t\ttimer at 101e3000 {\n" + " \t\ttimer@101e3000 {\n" " \t\t\tcompatible = \"arm,sp804\", \"arm,primecell\";\n" " \t\t\treg = <0x101e3000 0x1000>;\n" " \t\t\tinterrupts = <5>;\n" @@ -148,7 +153,7 @@ "+\t\t\tclock-names = \"tmrclk\", \"apb_pclk\";\n" " \t\t};\n" " \n" - " \t\tgpio0: gpio at 101e4000 {\n" + " \t\tgpio0: gpio@101e4000 {\n" "@@ -146,6 +202,8 @@\n" " \t\t\t#gpio-cells = <2>;\n" " \t\t\tinterrupt-controller;\n" @@ -157,7 +162,7 @@ "+\t\t\tclock-names = \"apb_pclk\";\n" " \t\t};\n" " \n" - " \t\tgpio1: gpio at 101e5000 {\n" + " \t\tgpio1: gpio@101e5000 {\n" "@@ -156,24 +214,32 @@\n" " \t\t\t#gpio-cells = <2>;\n" " \t\t\tinterrupt-controller;\n" @@ -166,7 +171,7 @@ "+\t\t\tclock-names = \"apb_pclk\";\n" " \t\t};\n" " \n" - " \t\trtc at 101e8000 {\n" + " \t\trtc@101e8000 {\n" " \t\t\tcompatible = \"arm,pl030\", \"arm,primecell\";\n" " \t\t\treg = <0x101e8000 0x1000>;\n" " \t\t\tinterrupts = <10>;\n" @@ -174,7 +179,7 @@ "+\t\t\tclock-names = \"apb_pclk\";\n" " \t\t};\n" " \n" - " \t\tsci at 101f0000 {\n" + " \t\tsci@101f0000 {\n" " \t\t\tcompatible = \"arm,primecell\";\n" " \t\t\treg = <0x101f0000 0x1000>;\n" " \t\t\tinterrupts = <15>;\n" @@ -182,7 +187,7 @@ "+\t\t\tclock-names = \"apb_pclk\";\n" " \t\t};\n" " \n" - " \t\tssp at 101f4000 {\n" + " \t\tssp@101f4000 {\n" " \t\t\tcompatible = \"arm,pl022\", \"arm,primecell\";\n" " \t\t\treg = <0x101f4000 0x1000>;\n" " \t\t\tinterrupts = <11>;\n" @@ -198,14 +203,14 @@ "+\t\t\t\tclocks = <&pclk>;\n" "+\t\t\t\tclock-names = \"apb_pclk\";\n" " \t\t\t};\n" - " \t\t\tmmc at 5000 {\n" + " \t\t\tmmc@5000 {\n" " \t\t\t\tcompatible = \"arm,pl180\", \"arm,primecell\";\n" " \t\t\t\treg = < 0x5000 0x1000>;\n" " \t\t\t\tinterrupts-extended = <&vic 22 &sic 2>;\n" "+\t\t\t\tclocks = <&osc24M>, <&pclk>;\n" "+\t\t\t\tclock-names = \"mclk\", \"apb_pclk\";\n" " \t\t\t};\n" - " \t\t\tkmi at 6000 {\n" + " \t\t\tkmi@6000 {\n" " \t\t\t\tcompatible = \"arm,pl050\", \"arm,primecell\";\n" " \t\t\t\treg = <0x6000 0x1000>;\n" " \t\t\t\tinterrupt-parent = <&sic>;\n" @@ -213,7 +218,7 @@ "+\t\t\t\tclocks = <&osc24M>, <&pclk>;\n" "+\t\t\t\tclock-names = \"KMIREFCLK\", \"apb_pclk\";\n" " \t\t\t};\n" - " \t\t\tkmi at 7000 {\n" + " \t\t\tkmi@7000 {\n" " \t\t\t\tcompatible = \"arm,pl050\", \"arm,primecell\";\n" " \t\t\t\treg = <0x7000 0x1000>;\n" " \t\t\t\tinterrupt-parent = <&sic>;\n" @@ -235,7 +240,7 @@ "+\t\t\tclock-names = \"apb_pclk\";\n" " \t\t};\n" " \n" - " \t\tgpio3: gpio at 101e7000 {\n" + " \t\tgpio3: gpio@101e7000 {\n" "@@ -23,6 +25,8 @@\n" " \t\t\t#gpio-cells = <2>;\n" " \t\t\tinterrupt-controller;\n" @@ -252,7 +257,7 @@ "+\t\t\t\tclocks = <&osc24M>, <&pclk>;\n" "+\t\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" " \t\t\t};\n" - " \t\t\tsci at a000 {\n" + " \t\t\tsci@a000 {\n" " \t\t\t\tcompatible = \"arm,primecell\";\n" " \t\t\t\treg = <0xa000 0x1000>;\n" " \t\t\t\tinterrupt-parent = <&sic>;\n" @@ -260,7 +265,7 @@ "+\t\t\t\tclocks = <&osc24M>;\n" "+\t\t\t\tclock-names = \"apb_pclk\";\n" " \t\t\t};\n" - " \t\t\tmmc at b000 {\n" + " \t\t\tmmc@b000 {\n" " \t\t\t\tcompatible = \"arm,pl180\", \"arm,primecell\";\n" " \t\t\t\treg = <0xb000 0x1000>;\n" " \t\t\t\tinterrupts-extended = <&vic 23 &sic 2>;\n" @@ -270,6 +275,11 @@ " \t\t};\n" " \t};\n" "-- \n" - 1.9.1 + "1.9.1\n" + "\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -4425ea798709e89f53dbd7cf1a80cc295dc4f4ee95a780bd27243826b39d89cc +7c511daa5c49a1cf6578b87768ddcb6aba6bf67ec3c803640274353972f8806c
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