From mboxrd@z Thu Jan 1 00:00:00 1970 From: Benjamin Herrenschmidt Subject: Re: ast2400 woes Date: Sat, 07 Jun 2014 17:16:29 +1000 Message-ID: <1402125389.3247.289.camel@pasglop> References: <1402054302.3247.242.camel@pasglop> <1402096812.3247.274.camel@pasglop> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by gabe.freedesktop.org (Postfix) with ESMTP id F3A1A6E47D for ; Sat, 7 Jun 2014 00:16:41 -0700 (PDT) In-Reply-To: <1402096812.3247.274.camel@pasglop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Dave Airlie Cc: YC Chen , dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org On Sat, 2014-06-07 at 09:20 +1000, Benjamin Herrenschmidt wrote: > IE. Is there a reason why bASTIsVGAEnabled() and vASTEnableVGAMMIO > use the IO ports ? The latter reads 0x43 and writes 0x43 and 0x42, > can it be made to always use MMIO 0x3c3 and write 0x3c3 and 0x3c2 ? > > On my AST2400 at least, even when MMIO is disabled, 0x3c3 still > responds so it works but is that valid for all chips ? Or do I need > to favor the PIO path if PIO is available in that case for older > chipsets ? Note: I have it working now with a couple of patches that i'll send when I've cleaned them up, though I still need answers to the earlier questions so we can make sure we don't break earlier chipset support on x86. However, YC, the Endian control bits in extended CRTC register A2 seem to have no effect at all. With a big endian kernel I get the wrong endian on graphics regardless of the setting of that register ! Is endian swapping supported on the AST2400 ? Also what is the exact effect of that register ? Does it affect access from PCI to the framebuffer or does it affect the way the CRTC consumes pixels from the framebuffer ? Is is supposed to have an effect on register accesses ? Cheers, Ben.