From mboxrd@z Thu Jan 1 00:00:00 1970 From: deepak.s@linux.intel.com Subject: [PATCH 0/7] Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt Date: Thu, 10 Jul 2014 13:16:20 +0530 Message-ID: <1404978387-28180-1-git-send-email-deepak.s@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 0F7606E657 for ; Wed, 9 Jul 2014 00:51:45 -0700 (PDT) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org From: Deepak S Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt for verifying the freq on VLV and CHV Deepak S (7): drm/i915: Read guaranteed freq for valleyview drm/i915: Add RP0/RP1/RPn render P state thresholds in VLV sysfs drm/i915: keep freq/opcode conversion function more generic drm/i915: populate mem_freq/cz_clock for chv drm/i915: CHV GPU frequency to opcode functions drm/i915/chv: Add basic PM interrupt support for CHV drm/i915: Add RP1 render P state thresholds in CHV drivers/gpu/drm/i915/i915_debugfs.c | 14 +-- drivers/gpu/drm/i915/i915_drv.h | 5 +- drivers/gpu/drm/i915/i915_irq.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/i915_sysfs.c | 30 +++++-- drivers/gpu/drm/i915/intel_pm.c | 164 +++++++++++++++++++++++++++++++++--- 6 files changed, 189 insertions(+), 32 deletions(-) -- 1.9.1