From: Alvise Rigo <a.rigo@virtualopensystems.com>
To: qemu-devel@nongnu.org, rob.herring@linaro.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
tech@virtualopensystems.com,
Alvise Rigo <a.rigo@virtualopensystems.com>
Subject: [Qemu-devel] [RFC PATCH 2/8] mach-virt: improve PCI memory topology definition
Date: Fri, 11 Jul 2014 09:21:04 +0200 [thread overview]
Message-ID: <1405063270-18902-3-git-send-email-a.rigo@virtualopensystems.com> (raw)
In-Reply-To: <1405063270-18902-1-git-send-email-a.rigo@virtualopensystems.com>
Some of the unnecessary redundancy here will be decreased later in this
series.
Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com>
---
hw/arm/virt.c | 37 +++++++++++++++++++++++++------------
1 file changed, 25 insertions(+), 12 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index ed9fc7a..c93152f 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -42,7 +42,6 @@
#include "qemu/bitops.h"
#include "qemu/error-report.h"
-#define NUM_VIRTIO_TRANSPORTS 32
/* Number of external interrupt lines to configure the GIC with */
#define NUM_IRQS 128
@@ -65,8 +64,14 @@ enum {
VIRT_GIC_DIST,
VIRT_GIC_CPU,
VIRT_UART,
+#define VIRT_UART_IRQS 16
VIRT_MMIO,
+#define NUM_VIRTIO_TRANSPORTS 32
+#define VIRTIO_BASE_IRQ VIRT_UART_IRQS
VIRT_PCI_CFG,
+ VIRT_PCI_IO,
+ VIRT_PCI_MEM,
+#define PCI_BASE_IRQ (VIRTIO_BASE_IRQ + NUM_VIRTIO_TRANSPORTS - 1)
};
typedef struct MemMapEntry {
@@ -108,12 +113,15 @@ static const MemMapEntry a15memmap[] = {
/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
/* 0x10000000 .. 0x40000000 reserved for PCI */
[VIRT_PCI_CFG] = { 0x10000000, 0x01000000 },
+ [VIRT_PCI_IO] = { 0x11000000, 0x00010000 },
+ [VIRT_PCI_MEM] = { 0x12000000, 0x2e000000 },
[VIRT_MEM] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 },
};
static const int a15irqmap[] = {
[VIRT_UART] = 1,
- [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
+ [VIRT_MMIO] = VIRTIO_BASE_IRQ, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
+ [VIRT_PCI_CFG] = PCI_BASE_IRQ,
};
static VirtBoardInfo machines[] = {
@@ -351,10 +359,14 @@ static void create_pci_host(const VirtBoardInfo *vbi, qemu_irq *pic)
SysBusDevice *busdev;
uint32_t gic_phandle;
char *nodename;
- hwaddr base = vbi->memmap[VIRT_PCI_CFG].base;
- hwaddr size = vbi->memmap[VIRT_PCI_CFG].size;
-
- nodename = g_strdup_printf("/pci@%" PRIx64, base);
+ hwaddr cfg_base = vbi->memmap[VIRT_PCI_CFG].base;
+ hwaddr cfg_size = vbi->memmap[VIRT_PCI_CFG].size;
+ hwaddr io_base = vbi->memmap[VIRT_PCI_IO].base;
+ hwaddr io_size = vbi->memmap[VIRT_PCI_IO].size;
+ hwaddr mem_base = vbi->memmap[VIRT_PCI_MEM].base;
+ hwaddr mem_size = vbi->memmap[VIRT_PCI_MEM].size;
+
+ nodename = g_strdup_printf("/pci@%" PRIx64, cfg_base);
qemu_fdt_add_subnode(vbi->fdt, nodename);
qemu_fdt_setprop_string(vbi->fdt, nodename, "compatible",
"pci-host-cam-generic");
@@ -363,11 +375,12 @@ static void create_pci_host(const VirtBoardInfo *vbi, qemu_irq *pic)
qemu_fdt_setprop_cell(vbi->fdt, nodename, "#size-cells", 0x2);
qemu_fdt_setprop_cell(vbi->fdt, nodename, "#interrupt-cells", 0x1);
- qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 2, base, 2, size);
+ qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg", 2, cfg_base,
+ 2, cfg_size);
qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges",
- 1, 0x01000000, 2, 0x00000000, 2, 0x11000000, 2, 0x00010000,
- 1, 0x02000000, 2, 0x12000000, 2, 0x12000000, 2, 0x2e000000);
+ 1, 0x01000000, 2, 0x00000000, 2, io_base, 2, io_size,
+ 1, 0x02000000, 2, 0x12000000, 2, mem_size, 2, mem_size);
gic_phandle = qemu_fdt_get_phandle(vbi->fdt, "/intc");
qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "interrupt-map-mask",
@@ -381,9 +394,9 @@ static void create_pci_host(const VirtBoardInfo *vbi, qemu_irq *pic)
dev = qdev_create(NULL, "generic_pci");
busdev = SYS_BUS_DEVICE(dev);
qdev_init_nofail(dev);
- sysbus_mmio_map(busdev, 0, base); /* PCI config */
- sysbus_mmio_map(busdev, 1, 0x11000000); /* PCI I/O */
- sysbus_mmio_map(busdev, 2, 0x12000000); /* PCI memory window */
+ sysbus_mmio_map(busdev, 0, cfg_base); /* PCI config */
+ sysbus_mmio_map(busdev, 1, io_base); /* PCI I/O */
+ sysbus_mmio_map(busdev, 2, mem_base); /* PCI memory window */
sysbus_connect_irq(busdev, 0, pic[4]);
sysbus_connect_irq(busdev, 1, pic[5]);
sysbus_connect_irq(busdev, 2, pic[6]);
--
1.9.1
next prev parent reply other threads:[~2014-07-11 7:21 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-11 7:21 [Qemu-devel] [RFC PATCH 0/8] Add Generic PCI host device update Alvise Rigo
2014-07-11 7:21 ` [Qemu-devel] [RFC PATCH 1/8] mach-virt: move GIC inside mach-virt structure Alvise Rigo
2014-07-11 7:21 ` Alvise Rigo [this message]
2014-07-11 7:21 ` [Qemu-devel] [RFC PATCH 3/8] QEMUMachine: finalize_dt function Alvise Rigo
2014-07-11 7:21 ` [Qemu-devel] [RFC PATCH 4/8] generic_pci: create header file Alvise Rigo
2014-07-11 7:21 ` [Qemu-devel] [RFC PATCH 5/8] generic_pci: create own map irq function Alvise Rigo
2014-07-11 7:21 ` [Qemu-devel] [RFC PATCH 6/8] generic_pci: generate dt node after devices init Alvise Rigo
2014-11-05 12:26 ` Claudio Fontana
2014-11-06 10:27 ` alvise rigo
2014-07-11 7:21 ` [Qemu-devel] [RFC PATCH 7/8] generic_pci: realize device with machine data Alvise Rigo
2014-07-11 7:21 ` [Qemu-devel] [RFC PATCH 8/8] generic_pci: add interrupt map structures Alvise Rigo
2014-07-11 9:09 ` [Qemu-devel] [RFC PATCH 0/8] Add Generic PCI host device update Peter Maydell
2014-07-11 9:28 ` Alvise Rigo
2014-07-13 14:28 ` Rob Herring
2014-09-09 16:35 ` Claudio Fontana
2014-09-10 7:31 ` alvise rigo
2014-11-05 10:23 ` Claudio Fontana
2014-11-05 11:09 ` alvise rigo
2014-11-07 15:40 ` Claudio Fontana
2014-11-10 10:00 ` alvise rigo
2014-11-11 3:24 ` Ming Lei
2014-11-11 4:22 ` Ming Lei
2014-11-11 10:26 ` Claudio Fontana
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