From mboxrd@z Thu Jan 1 00:00:00 1970 From: AlisonWang Date: Tue, 19 Aug 2014 19:39:37 -0700 (PDT) Subject: [U-Boot] [PATCH v5 01/16] arm: ls102xa: Add Freescale LS102xA SoC support In-Reply-To: <20140819111944.GH3302@leverpostej> References: <1408416905-19771-1-git-send-email-b18965@freescale.com> <1408416905-19771-2-git-send-email-b18965@freescale.com> <20140819111944.GH3302@leverpostej> Message-ID: <1408502376990-187075.post@n7.nabble.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi, Mark, On Tue, Aug 19, 2014 at 03:54:50AM +0100, Alison Wang wrote: > +int timer_init(void) > +{ > + struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; > + unsigned long ctrl, val, freq; > + > + /* Enable System Counter */ > + writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr); > + > + freq = GENERIC_TIMER_CLK; > + asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); Is CNTFRQ initialised for both CPUs? [Alison Wang] No, only one CPU is booted now. If the CPUs are booted at PL1 rather than PL2, is CNTVOFF initialised to the same value on both CPUs? [Alison Wang] CNTVOFF is not initialized in the current secure mode. When we add virtualization support and switch to non-secure mode, we will initialize CNTVOFF to zero on both CPUs. Thanks. Alison -- View this message in context: http://u-boot.10912.n7.nabble.com/PATCH-v5-0-16-arm-ls102xa-Add-Freescale-LS102xA-SoC-and-LS1021AQDS-TWR-board-support-tp186978p187075.html Sent from the U-Boot mailing list archive at Nabble.com.