diff for duplicates of <1409899692-1455-6-git-send-email-rric@kernel.org> diff --git a/a/1.txt b/N1/1.txt index 6ae86ea..beaee1b 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -110,56 +110,56 @@ index c0aceef7f5b3..000000000000 - #address-cells = <2>; - #size-cells = <0>; - -- cpu@000 { +- cpu at 000 { - device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; - reg = <0x0 0x000>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - }; -- cpu@001 { +- cpu at 001 { - device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; - reg = <0x0 0x001>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - }; -- cpu@100 { +- cpu at 100 { - device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; - reg = <0x0 0x100>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - }; -- cpu@101 { +- cpu at 101 { - device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; - reg = <0x0 0x101>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - }; -- cpu@200 { +- cpu at 200 { - device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; - reg = <0x0 0x200>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - }; -- cpu@201 { +- cpu at 201 { - device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; - reg = <0x0 0x201>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - }; -- cpu@300 { +- cpu at 300 { - device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; - reg = <0x0 0x300>; - enable-method = "spin-table"; - cpu-release-addr = <0x1 0x0000fff8>; - }; -- cpu@301 { +- cpu at 301 { - device_type = "cpu"; - compatible = "apm,potenza", "arm,armv8"; - reg = <0x0 0x301>; @@ -168,7 +168,7 @@ index c0aceef7f5b3..000000000000 - }; - }; - -- gic: interrupt-controller@78010000 { +- gic: interrupt-controller at 78010000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; @@ -205,7 +205,7 @@ index c0aceef7f5b3..000000000000 - clock-output-names = "refclk"; - }; - -- pcppll: pcppll@17000100 { +- pcppll: pcppll at 17000100 { - compatible = "apm,xgene-pcppll-clock"; - #clock-cells = <1>; - clocks = <&refclk 0>; @@ -215,7 +215,7 @@ index c0aceef7f5b3..000000000000 - type = <0>; - }; - -- socpll: socpll@17000120 { +- socpll: socpll at 17000120 { - compatible = "apm,xgene-socpll-clock"; - #clock-cells = <1>; - clocks = <&refclk 0>; @@ -267,7 +267,7 @@ index c0aceef7f5b3..000000000000 - clock-output-names = "menetclk"; - }; - -- sataphy1clk: sataphy1clk@1f21c000 { +- sataphy1clk: sataphy1clk at 1f21c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; @@ -281,7 +281,7 @@ index c0aceef7f5b3..000000000000 - enable-mask = <0x06>; - }; - -- sataphy2clk: sataphy1clk@1f22c000 { +- sataphy2clk: sataphy1clk at 1f22c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; @@ -295,7 +295,7 @@ index c0aceef7f5b3..000000000000 - enable-mask = <0x06>; - }; - -- sataphy3clk: sataphy1clk@1f23c000 { +- sataphy3clk: sataphy1clk at 1f23c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; @@ -309,7 +309,7 @@ index c0aceef7f5b3..000000000000 - enable-mask = <0x06>; - }; - -- sata01clk: sata01clk@1f21c000 { +- sata01clk: sata01clk at 1f21c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; @@ -322,7 +322,7 @@ index c0aceef7f5b3..000000000000 - enable-mask = <0x39>; - }; - -- sata23clk: sata23clk@1f22c000 { +- sata23clk: sata23clk at 1f22c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; @@ -335,7 +335,7 @@ index c0aceef7f5b3..000000000000 - enable-mask = <0x39>; - }; - -- sata45clk: sata45clk@1f23c000 { +- sata45clk: sata45clk at 1f23c000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; @@ -348,7 +348,7 @@ index c0aceef7f5b3..000000000000 - enable-mask = <0x39>; - }; - -- rtcclk: rtcclk@17000000 { +- rtcclk: rtcclk at 17000000 { - compatible = "apm,xgene-device-clock"; - #clock-cells = <1>; - clocks = <&socplldiv2 0>; @@ -362,7 +362,7 @@ index c0aceef7f5b3..000000000000 - }; - }; - -- serial0: serial@1c020000 { +- serial0: serial at 1c020000 { - status = "disabled"; - device_type = "serial"; - compatible = "ns16550a"; @@ -373,7 +373,7 @@ index c0aceef7f5b3..000000000000 - interrupts = <0x0 0x4c 0x4>; - }; - -- serial1: serial@1c021000 { +- serial1: serial at 1c021000 { - status = "disabled"; - device_type = "serial"; - compatible = "ns16550a"; @@ -384,7 +384,7 @@ index c0aceef7f5b3..000000000000 - interrupts = <0x0 0x4d 0x4>; - }; - -- serial2: serial@1c022000 { +- serial2: serial at 1c022000 { - status = "disabled"; - device_type = "serial"; - compatible = "ns16550a"; @@ -395,7 +395,7 @@ index c0aceef7f5b3..000000000000 - interrupts = <0x0 0x4e 0x4>; - }; - -- serial3: serial@1c023000 { +- serial3: serial at 1c023000 { - status = "disabled"; - device_type = "serial"; - compatible = "ns16550a"; @@ -406,7 +406,7 @@ index c0aceef7f5b3..000000000000 - interrupts = <0x0 0x4f 0x4>; - }; - -- phy1: phy@1f21a000 { +- phy1: phy at 1f21a000 { - compatible = "apm,xgene-phy"; - reg = <0x0 0x1f21a000 0x0 0x100>; - #phy-cells = <1>; @@ -416,7 +416,7 @@ index c0aceef7f5b3..000000000000 - apm,tx-eye-tuning = <2 10 10 2 10 10>; - }; - -- phy2: phy@1f22a000 { +- phy2: phy at 1f22a000 { - compatible = "apm,xgene-phy"; - reg = <0x0 0x1f22a000 0x0 0x100>; - #phy-cells = <1>; @@ -426,7 +426,7 @@ index c0aceef7f5b3..000000000000 - apm,tx-eye-tuning = <1 10 10 2 10 10>; - }; - -- phy3: phy@1f23a000 { +- phy3: phy at 1f23a000 { - compatible = "apm,xgene-phy"; - reg = <0x0 0x1f23a000 0x0 0x100>; - #phy-cells = <1>; @@ -436,7 +436,7 @@ index c0aceef7f5b3..000000000000 - apm,tx-eye-tuning = <2 10 10 2 10 10>; - }; - -- sata1: sata@1a000000 { +- sata1: sata at 1a000000 { - compatible = "apm,xgene-ahci"; - reg = <0x0 0x1a000000 0x0 0x1000>, - <0x0 0x1f210000 0x0 0x1000>, @@ -451,7 +451,7 @@ index c0aceef7f5b3..000000000000 - phy-names = "sata-phy"; - }; - -- sata2: sata@1a400000 { +- sata2: sata at 1a400000 { - compatible = "apm,xgene-ahci"; - reg = <0x0 0x1a400000 0x0 0x1000>, - <0x0 0x1f220000 0x0 0x1000>, @@ -466,7 +466,7 @@ index c0aceef7f5b3..000000000000 - phy-names = "sata-phy"; - }; - -- sata3: sata@1a800000 { +- sata3: sata at 1a800000 { - compatible = "apm,xgene-ahci"; - reg = <0x0 0x1a800000 0x0 0x1000>, - <0x0 0x1f230000 0x0 0x1000>, @@ -480,7 +480,7 @@ index c0aceef7f5b3..000000000000 - phy-names = "sata-phy"; - }; - -- rtc: rtc@10510000 { +- rtc: rtc at 10510000 { - compatible = "apm,xgene-rtc"; - reg = <0x0 0x10510000 0x0 0x400>; - interrupts = <0x0 0x46 0x4>; @@ -488,7 +488,7 @@ index c0aceef7f5b3..000000000000 - clocks = <&rtcclk 0>; - }; - -- menet: ethernet@17020000 { +- menet: ethernet at 17020000 { - compatible = "apm,xgene-enet"; - status = "disabled"; - reg = <0x0 0x17020000 0x0 0xd100>, @@ -505,7 +505,7 @@ index c0aceef7f5b3..000000000000 - compatible = "apm,xgene-mdio"; - #address-cells = <1>; - #size-cells = <0>; -- menetphy: menetphy@3 { +- menetphy: menetphy at 3 { - compatible = "ethernet-phy-id001c.c915"; - reg = <0x3>; - }; @@ -592,56 +592,56 @@ index 000000000000..c0aceef7f5b3 + #address-cells = <2>; + #size-cells = <0>; + -+ cpu@000 { ++ cpu at 000 { + device_type = "cpu"; + compatible = "apm,potenza", "arm,armv8"; + reg = <0x0 0x000>; + enable-method = "spin-table"; + cpu-release-addr = <0x1 0x0000fff8>; + }; -+ cpu@001 { ++ cpu at 001 { + device_type = "cpu"; + compatible = "apm,potenza", "arm,armv8"; + reg = <0x0 0x001>; + enable-method = "spin-table"; + cpu-release-addr = <0x1 0x0000fff8>; + }; -+ cpu@100 { ++ cpu at 100 { + device_type = "cpu"; + compatible = "apm,potenza", "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0x1 0x0000fff8>; + }; -+ cpu@101 { ++ cpu at 101 { + device_type = "cpu"; + compatible = "apm,potenza", "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "spin-table"; + cpu-release-addr = <0x1 0x0000fff8>; + }; -+ cpu@200 { ++ cpu at 200 { + device_type = "cpu"; + compatible = "apm,potenza", "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "spin-table"; + cpu-release-addr = <0x1 0x0000fff8>; + }; -+ cpu@201 { ++ cpu at 201 { + device_type = "cpu"; + compatible = "apm,potenza", "arm,armv8"; + reg = <0x0 0x201>; + enable-method = "spin-table"; + cpu-release-addr = <0x1 0x0000fff8>; + }; -+ cpu@300 { ++ cpu at 300 { + device_type = "cpu"; + compatible = "apm,potenza", "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "spin-table"; + cpu-release-addr = <0x1 0x0000fff8>; + }; -+ cpu@301 { ++ cpu at 301 { + device_type = "cpu"; + compatible = "apm,potenza", "arm,armv8"; + reg = <0x0 0x301>; @@ -650,7 +650,7 @@ index 000000000000..c0aceef7f5b3 + }; + }; + -+ gic: interrupt-controller@78010000 { ++ gic: interrupt-controller at 78010000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; @@ -687,7 +687,7 @@ index 000000000000..c0aceef7f5b3 + clock-output-names = "refclk"; + }; + -+ pcppll: pcppll@17000100 { ++ pcppll: pcppll at 17000100 { + compatible = "apm,xgene-pcppll-clock"; + #clock-cells = <1>; + clocks = <&refclk 0>; @@ -697,7 +697,7 @@ index 000000000000..c0aceef7f5b3 + type = <0>; + }; + -+ socpll: socpll@17000120 { ++ socpll: socpll at 17000120 { + compatible = "apm,xgene-socpll-clock"; + #clock-cells = <1>; + clocks = <&refclk 0>; @@ -749,7 +749,7 @@ index 000000000000..c0aceef7f5b3 + clock-output-names = "menetclk"; + }; + -+ sataphy1clk: sataphy1clk@1f21c000 { ++ sataphy1clk: sataphy1clk at 1f21c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; @@ -763,7 +763,7 @@ index 000000000000..c0aceef7f5b3 + enable-mask = <0x06>; + }; + -+ sataphy2clk: sataphy1clk@1f22c000 { ++ sataphy2clk: sataphy1clk at 1f22c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; @@ -777,7 +777,7 @@ index 000000000000..c0aceef7f5b3 + enable-mask = <0x06>; + }; + -+ sataphy3clk: sataphy1clk@1f23c000 { ++ sataphy3clk: sataphy1clk at 1f23c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; @@ -791,7 +791,7 @@ index 000000000000..c0aceef7f5b3 + enable-mask = <0x06>; + }; + -+ sata01clk: sata01clk@1f21c000 { ++ sata01clk: sata01clk at 1f21c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; @@ -804,7 +804,7 @@ index 000000000000..c0aceef7f5b3 + enable-mask = <0x39>; + }; + -+ sata23clk: sata23clk@1f22c000 { ++ sata23clk: sata23clk at 1f22c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; @@ -817,7 +817,7 @@ index 000000000000..c0aceef7f5b3 + enable-mask = <0x39>; + }; + -+ sata45clk: sata45clk@1f23c000 { ++ sata45clk: sata45clk at 1f23c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; @@ -830,7 +830,7 @@ index 000000000000..c0aceef7f5b3 + enable-mask = <0x39>; + }; + -+ rtcclk: rtcclk@17000000 { ++ rtcclk: rtcclk at 17000000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; @@ -844,7 +844,7 @@ index 000000000000..c0aceef7f5b3 + }; + }; + -+ serial0: serial@1c020000 { ++ serial0: serial at 1c020000 { + status = "disabled"; + device_type = "serial"; + compatible = "ns16550a"; @@ -855,7 +855,7 @@ index 000000000000..c0aceef7f5b3 + interrupts = <0x0 0x4c 0x4>; + }; + -+ serial1: serial@1c021000 { ++ serial1: serial at 1c021000 { + status = "disabled"; + device_type = "serial"; + compatible = "ns16550a"; @@ -866,7 +866,7 @@ index 000000000000..c0aceef7f5b3 + interrupts = <0x0 0x4d 0x4>; + }; + -+ serial2: serial@1c022000 { ++ serial2: serial at 1c022000 { + status = "disabled"; + device_type = "serial"; + compatible = "ns16550a"; @@ -877,7 +877,7 @@ index 000000000000..c0aceef7f5b3 + interrupts = <0x0 0x4e 0x4>; + }; + -+ serial3: serial@1c023000 { ++ serial3: serial at 1c023000 { + status = "disabled"; + device_type = "serial"; + compatible = "ns16550a"; @@ -888,7 +888,7 @@ index 000000000000..c0aceef7f5b3 + interrupts = <0x0 0x4f 0x4>; + }; + -+ phy1: phy@1f21a000 { ++ phy1: phy at 1f21a000 { + compatible = "apm,xgene-phy"; + reg = <0x0 0x1f21a000 0x0 0x100>; + #phy-cells = <1>; @@ -898,7 +898,7 @@ index 000000000000..c0aceef7f5b3 + apm,tx-eye-tuning = <2 10 10 2 10 10>; + }; + -+ phy2: phy@1f22a000 { ++ phy2: phy at 1f22a000 { + compatible = "apm,xgene-phy"; + reg = <0x0 0x1f22a000 0x0 0x100>; + #phy-cells = <1>; @@ -908,7 +908,7 @@ index 000000000000..c0aceef7f5b3 + apm,tx-eye-tuning = <1 10 10 2 10 10>; + }; + -+ phy3: phy@1f23a000 { ++ phy3: phy at 1f23a000 { + compatible = "apm,xgene-phy"; + reg = <0x0 0x1f23a000 0x0 0x100>; + #phy-cells = <1>; @@ -918,7 +918,7 @@ index 000000000000..c0aceef7f5b3 + apm,tx-eye-tuning = <2 10 10 2 10 10>; + }; + -+ sata1: sata@1a000000 { ++ sata1: sata at 1a000000 { + compatible = "apm,xgene-ahci"; + reg = <0x0 0x1a000000 0x0 0x1000>, + <0x0 0x1f210000 0x0 0x1000>, @@ -933,7 +933,7 @@ index 000000000000..c0aceef7f5b3 + phy-names = "sata-phy"; + }; + -+ sata2: sata@1a400000 { ++ sata2: sata at 1a400000 { + compatible = "apm,xgene-ahci"; + reg = <0x0 0x1a400000 0x0 0x1000>, + <0x0 0x1f220000 0x0 0x1000>, @@ -948,7 +948,7 @@ index 000000000000..c0aceef7f5b3 + phy-names = "sata-phy"; + }; + -+ sata3: sata@1a800000 { ++ sata3: sata at 1a800000 { + compatible = "apm,xgene-ahci"; + reg = <0x0 0x1a800000 0x0 0x1000>, + <0x0 0x1f230000 0x0 0x1000>, @@ -962,7 +962,7 @@ index 000000000000..c0aceef7f5b3 + phy-names = "sata-phy"; + }; + -+ rtc: rtc@10510000 { ++ rtc: rtc at 10510000 { + compatible = "apm,xgene-rtc"; + reg = <0x0 0x10510000 0x0 0x400>; + interrupts = <0x0 0x46 0x4>; @@ -970,7 +970,7 @@ index 000000000000..c0aceef7f5b3 + clocks = <&rtcclk 0>; + }; + -+ menet: ethernet@17020000 { ++ menet: ethernet at 17020000 { + compatible = "apm,xgene-enet"; + status = "disabled"; + reg = <0x0 0x17020000 0x0 0xd100>, @@ -987,7 +987,7 @@ index 000000000000..c0aceef7f5b3 + compatible = "apm,xgene-mdio"; + #address-cells = <1>; + #size-cells = <0>; -+ menetphy: menetphy@3 { ++ menetphy: menetphy at 3 { + compatible = "ethernet-phy-id001c.c915"; + reg = <0x3>; + }; @@ -1044,28 +1044,28 @@ index 000000000000..4a060906809d + #address-cells = <2>; + #size-cells = <0>; + -+ cpu@0 { ++ cpu at 0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; -+ cpu@1 { ++ cpu at 1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; -+ cpu@2 { ++ cpu at 2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; -+ cpu@3 { ++ cpu at 3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; @@ -1074,13 +1074,13 @@ index 000000000000..4a060906809d + }; + }; + -+ memory@80000000 { ++ memory at 80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + -+ gic: interrupt-controller@2c001000 { ++ gic: interrupt-controller at 2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; @@ -1168,7 +1168,7 @@ index 000000000000..4a060906809d + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + -+ ethernet@2,02000000 { ++ ethernet at 2,02000000 { + compatible = "smsc,lan91c111"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; @@ -1195,18 +1195,18 @@ index 000000000000..4a060906809d + clock-output-names = "v2m:refclk32khz"; + }; + -+ iofpga@3,00000000 { ++ iofpga at 3,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + -+ v2m_sysreg: sysreg@010000 { ++ v2m_sysreg: sysreg at 010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + }; + -+ v2m_serial0: uart@090000 { ++ v2m_serial0: uart at 090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; @@ -1214,7 +1214,7 @@ index 000000000000..4a060906809d + clock-names = "uartclk", "apb_pclk"; + }; + -+ v2m_serial1: uart@0a0000 { ++ v2m_serial1: uart at 0a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; @@ -1222,7 +1222,7 @@ index 000000000000..4a060906809d + clock-names = "uartclk", "apb_pclk"; + }; + -+ v2m_serial2: uart@0b0000 { ++ v2m_serial2: uart at 0b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; @@ -1230,7 +1230,7 @@ index 000000000000..4a060906809d + clock-names = "uartclk", "apb_pclk"; + }; + -+ v2m_serial3: uart@0c0000 { ++ v2m_serial3: uart at 0c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; @@ -1238,7 +1238,7 @@ index 000000000000..4a060906809d + clock-names = "uartclk", "apb_pclk"; + }; + -+ virtio_block@0130000 { ++ virtio_block at 0130000 { + compatible = "virtio,mmio"; + reg = <0x130000 0x200>; + interrupts = <42>; @@ -1285,28 +1285,28 @@ index 000000000000..572005ea2217 + #address-cells = <2>; + #size-cells = <0>; + -+ cpu@0 { ++ cpu at 0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; -+ cpu@1 { ++ cpu at 1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; -+ cpu@2 { ++ cpu at 2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; -+ cpu@3 { ++ cpu at 3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; @@ -1315,13 +1315,13 @@ index 000000000000..572005ea2217 + }; + }; + -+ memory@80000000 { ++ memory at 80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + -+ gic: interrupt-controller@2c001000 { ++ gic: interrupt-controller at 2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; @@ -1434,19 +1434,19 @@ index 000000000000..ac2cb2418025 + #interrupt-cells = <1>; + ranges; + -+ flash@0,00000000 { ++ flash at 0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <4 0x00000000 0x04000000>; + bank-width = <4>; + }; + -+ vram@2,00000000 { ++ vram at 2,00000000 { + compatible = "arm,vexpress-vram"; + reg = <2 0x00000000 0x00800000>; + }; + -+ ethernet@2,02000000 { ++ ethernet at 2,02000000 { + compatible = "smsc,lan91c111"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; @@ -1473,20 +1473,20 @@ index 000000000000..ac2cb2418025 + clock-output-names = "v2m:refclk32khz"; + }; + -+ iofpga@3,00000000 { ++ iofpga at 3,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + -+ v2m_sysreg: sysreg@010000 { ++ v2m_sysreg: sysreg at 010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + -+ v2m_sysctl: sysctl@020000 { ++ v2m_sysctl: sysctl at 020000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; @@ -1495,7 +1495,7 @@ index 000000000000..ac2cb2418025 + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + }; + -+ aaci@040000 { ++ aaci at 040000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x040000 0x1000>; + interrupts = <11>; @@ -1503,7 +1503,7 @@ index 000000000000..ac2cb2418025 + clock-names = "apb_pclk"; + }; + -+ mmci@050000 { ++ mmci at 050000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x050000 0x1000>; + interrupts = <9 10>; @@ -1515,7 +1515,7 @@ index 000000000000..ac2cb2418025 + clock-names = "mclk", "apb_pclk"; + }; + -+ kmi@060000 { ++ kmi at 060000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <12>; @@ -1523,7 +1523,7 @@ index 000000000000..ac2cb2418025 + clock-names = "KMIREFCLK", "apb_pclk"; + }; + -+ kmi@070000 { ++ kmi at 070000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <13>; @@ -1531,7 +1531,7 @@ index 000000000000..ac2cb2418025 + clock-names = "KMIREFCLK", "apb_pclk"; + }; + -+ v2m_serial0: uart@090000 { ++ v2m_serial0: uart at 090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; @@ -1539,7 +1539,7 @@ index 000000000000..ac2cb2418025 + clock-names = "uartclk", "apb_pclk"; + }; + -+ v2m_serial1: uart@0a0000 { ++ v2m_serial1: uart at 0a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; @@ -1547,7 +1547,7 @@ index 000000000000..ac2cb2418025 + clock-names = "uartclk", "apb_pclk"; + }; + -+ v2m_serial2: uart@0b0000 { ++ v2m_serial2: uart at 0b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; @@ -1555,7 +1555,7 @@ index 000000000000..ac2cb2418025 + clock-names = "uartclk", "apb_pclk"; + }; + -+ v2m_serial3: uart@0c0000 { ++ v2m_serial3: uart at 0c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; @@ -1563,7 +1563,7 @@ index 000000000000..ac2cb2418025 + clock-names = "uartclk", "apb_pclk"; + }; + -+ wdt@0f0000 { ++ wdt at 0f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x1000>; + interrupts = <0>; @@ -1571,7 +1571,7 @@ index 000000000000..ac2cb2418025 + clock-names = "wdogclk", "apb_pclk"; + }; + -+ v2m_timer01: timer@110000 { ++ v2m_timer01: timer at 110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x1000>; + interrupts = <2>; @@ -1579,7 +1579,7 @@ index 000000000000..ac2cb2418025 + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + -+ v2m_timer23: timer@120000 { ++ v2m_timer23: timer at 120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x1000>; + interrupts = <3>; @@ -1587,7 +1587,7 @@ index 000000000000..ac2cb2418025 + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + -+ rtc@170000 { ++ rtc at 170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x1000>; + interrupts = <4>; @@ -1595,7 +1595,7 @@ index 000000000000..ac2cb2418025 + clock-names = "apb_pclk"; + }; + -+ clcd@1f0000 { ++ clcd at 1f0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f0000 0x1000>; + interrupts = <14>; @@ -1603,14 +1603,14 @@ index 000000000000..ac2cb2418025 + clock-names = "clcdclk", "apb_pclk"; + }; + -+ virtio_block@0130000 { ++ virtio_block at 0130000 { + compatible = "virtio,mmio"; + reg = <0x130000 0x200>; + interrupts = <42>; + }; + }; + -+ v2m_fixed_3v3: fixedregulator@0 { ++ v2m_fixed_3v3: fixedregulator at 0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; @@ -1622,7 +1622,7 @@ index 000000000000..ac2cb2418025 + compatible = "arm,vexpress,config-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + -+ v2m_oscclk1: osc@1 { ++ v2m_oscclk1: osc at 1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; @@ -1631,27 +1631,27 @@ index 000000000000..ac2cb2418025 + clock-output-names = "v2m:oscclk1"; + }; + -+ reset@0 { ++ reset at 0 { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + -+ muxfpga@0 { ++ muxfpga at 0 { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + -+ shutdown@0 { ++ shutdown at 0 { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + -+ reboot@0 { ++ reboot at 0 { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + -+ dvimode@0 { ++ dvimode at 0 { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; @@ -1693,28 +1693,28 @@ index 4a060906809d..000000000000 - #address-cells = <2>; - #size-cells = <0>; - -- cpu@0 { +- cpu at 0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; - }; -- cpu@1 { +- cpu at 1 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; - }; -- cpu@2 { +- cpu at 2 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x2>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; - }; -- cpu@3 { +- cpu at 3 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x3>; @@ -1723,13 +1723,13 @@ index 4a060906809d..000000000000 - }; - }; - -- memory@80000000 { +- memory at 80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>, - <0x00000008 0x80000000 0 0x80000000>; - }; - -- gic: interrupt-controller@2c001000 { +- gic: interrupt-controller at 2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; @@ -1817,7 +1817,7 @@ index 4a060906809d..000000000000 - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - -- ethernet@2,02000000 { +- ethernet at 2,02000000 { - compatible = "smsc,lan91c111"; - reg = <2 0x02000000 0x10000>; - interrupts = <15>; @@ -1844,18 +1844,18 @@ index 4a060906809d..000000000000 - clock-output-names = "v2m:refclk32khz"; - }; - -- iofpga@3,00000000 { +- iofpga at 3,00000000 { - compatible = "arm,amba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - -- v2m_sysreg: sysreg@010000 { +- v2m_sysreg: sysreg at 010000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - }; - -- v2m_serial0: uart@090000 { +- v2m_serial0: uart at 090000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x090000 0x1000>; - interrupts = <5>; @@ -1863,7 +1863,7 @@ index 4a060906809d..000000000000 - clock-names = "uartclk", "apb_pclk"; - }; - -- v2m_serial1: uart@0a0000 { +- v2m_serial1: uart at 0a0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a0000 0x1000>; - interrupts = <6>; @@ -1871,7 +1871,7 @@ index 4a060906809d..000000000000 - clock-names = "uartclk", "apb_pclk"; - }; - -- v2m_serial2: uart@0b0000 { +- v2m_serial2: uart at 0b0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b0000 0x1000>; - interrupts = <7>; @@ -1879,7 +1879,7 @@ index 4a060906809d..000000000000 - clock-names = "uartclk", "apb_pclk"; - }; - -- v2m_serial3: uart@0c0000 { +- v2m_serial3: uart at 0c0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c0000 0x1000>; - interrupts = <8>; @@ -1887,7 +1887,7 @@ index 4a060906809d..000000000000 - clock-names = "uartclk", "apb_pclk"; - }; - -- virtio_block@0130000 { +- virtio_block at 0130000 { - compatible = "virtio,mmio"; - reg = <0x130000 0x200>; - interrupts = <42>; @@ -1934,28 +1934,28 @@ index 572005ea2217..000000000000 - #address-cells = <2>; - #size-cells = <0>; - -- cpu@0 { +- cpu at 0 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x0>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; - }; -- cpu@1 { +- cpu at 1 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x1>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; - }; -- cpu@2 { +- cpu at 2 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x2>; - enable-method = "spin-table"; - cpu-release-addr = <0x0 0x8000fff8>; - }; -- cpu@3 { +- cpu at 3 { - device_type = "cpu"; - compatible = "arm,armv8"; - reg = <0x0 0x3>; @@ -1964,13 +1964,13 @@ index 572005ea2217..000000000000 - }; - }; - -- memory@80000000 { +- memory at 80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0 0x80000000>, - <0x00000008 0x80000000 0 0x80000000>; - }; - -- gic: interrupt-controller@2c001000 { +- gic: interrupt-controller at 2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; @@ -2083,19 +2083,19 @@ index ac2cb2418025..000000000000 - #interrupt-cells = <1>; - ranges; - -- flash@0,00000000 { +- flash at 0,00000000 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <4 0x00000000 0x04000000>; - bank-width = <4>; - }; - -- vram@2,00000000 { +- vram at 2,00000000 { - compatible = "arm,vexpress-vram"; - reg = <2 0x00000000 0x00800000>; - }; - -- ethernet@2,02000000 { +- ethernet at 2,02000000 { - compatible = "smsc,lan91c111"; - reg = <2 0x02000000 0x10000>; - interrupts = <15>; @@ -2122,20 +2122,20 @@ index ac2cb2418025..000000000000 - clock-output-names = "v2m:refclk32khz"; - }; - -- iofpga@3,00000000 { +- iofpga at 3,00000000 { - compatible = "arm,amba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - -- v2m_sysreg: sysreg@010000 { +- v2m_sysreg: sysreg at 010000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - }; - -- v2m_sysctl: sysctl@020000 { +- v2m_sysctl: sysctl at 020000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; @@ -2144,7 +2144,7 @@ index ac2cb2418025..000000000000 - clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; - }; - -- aaci@040000 { +- aaci at 040000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x040000 0x1000>; - interrupts = <11>; @@ -2152,7 +2152,7 @@ index ac2cb2418025..000000000000 - clock-names = "apb_pclk"; - }; - -- mmci@050000 { +- mmci at 050000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x050000 0x1000>; - interrupts = <9 10>; @@ -2164,7 +2164,7 @@ index ac2cb2418025..000000000000 - clock-names = "mclk", "apb_pclk"; - }; - -- kmi@060000 { +- kmi at 060000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x060000 0x1000>; - interrupts = <12>; @@ -2172,7 +2172,7 @@ index ac2cb2418025..000000000000 - clock-names = "KMIREFCLK", "apb_pclk"; - }; - -- kmi@070000 { +- kmi at 070000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x070000 0x1000>; - interrupts = <13>; @@ -2180,7 +2180,7 @@ index ac2cb2418025..000000000000 - clock-names = "KMIREFCLK", "apb_pclk"; - }; - -- v2m_serial0: uart@090000 { +- v2m_serial0: uart at 090000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x090000 0x1000>; - interrupts = <5>; @@ -2188,7 +2188,7 @@ index ac2cb2418025..000000000000 - clock-names = "uartclk", "apb_pclk"; - }; - -- v2m_serial1: uart@0a0000 { +- v2m_serial1: uart at 0a0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a0000 0x1000>; - interrupts = <6>; @@ -2196,7 +2196,7 @@ index ac2cb2418025..000000000000 - clock-names = "uartclk", "apb_pclk"; - }; - -- v2m_serial2: uart@0b0000 { +- v2m_serial2: uart at 0b0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b0000 0x1000>; - interrupts = <7>; @@ -2204,7 +2204,7 @@ index ac2cb2418025..000000000000 - clock-names = "uartclk", "apb_pclk"; - }; - -- v2m_serial3: uart@0c0000 { +- v2m_serial3: uart at 0c0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c0000 0x1000>; - interrupts = <8>; @@ -2212,7 +2212,7 @@ index ac2cb2418025..000000000000 - clock-names = "uartclk", "apb_pclk"; - }; - -- wdt@0f0000 { +- wdt at 0f0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f0000 0x1000>; - interrupts = <0>; @@ -2220,7 +2220,7 @@ index ac2cb2418025..000000000000 - clock-names = "wdogclk", "apb_pclk"; - }; - -- v2m_timer01: timer@110000 { +- v2m_timer01: timer at 110000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x110000 0x1000>; - interrupts = <2>; @@ -2228,7 +2228,7 @@ index ac2cb2418025..000000000000 - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - -- v2m_timer23: timer@120000 { +- v2m_timer23: timer at 120000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x120000 0x1000>; - interrupts = <3>; @@ -2236,7 +2236,7 @@ index ac2cb2418025..000000000000 - clock-names = "timclken1", "timclken2", "apb_pclk"; - }; - -- rtc@170000 { +- rtc at 170000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x170000 0x1000>; - interrupts = <4>; @@ -2244,7 +2244,7 @@ index ac2cb2418025..000000000000 - clock-names = "apb_pclk"; - }; - -- clcd@1f0000 { +- clcd at 1f0000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f0000 0x1000>; - interrupts = <14>; @@ -2252,14 +2252,14 @@ index ac2cb2418025..000000000000 - clock-names = "clcdclk", "apb_pclk"; - }; - -- virtio_block@0130000 { +- virtio_block at 0130000 { - compatible = "virtio,mmio"; - reg = <0x130000 0x200>; - interrupts = <42>; - }; - }; - -- v2m_fixed_3v3: fixedregulator@0 { +- v2m_fixed_3v3: fixedregulator at 0 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; @@ -2271,7 +2271,7 @@ index ac2cb2418025..000000000000 - compatible = "arm,vexpress,config-bus"; - arm,vexpress,config-bridge = <&v2m_sysreg>; - -- v2m_oscclk1: osc@1 { +- v2m_oscclk1: osc at 1 { - /* CLCD clock */ - compatible = "arm,vexpress-osc"; - arm,vexpress-sysreg,func = <1 1>; @@ -2280,27 +2280,27 @@ index ac2cb2418025..000000000000 - clock-output-names = "v2m:oscclk1"; - }; - -- reset@0 { +- reset at 0 { - compatible = "arm,vexpress-reset"; - arm,vexpress-sysreg,func = <5 0>; - }; - -- muxfpga@0 { +- muxfpga at 0 { - compatible = "arm,vexpress-muxfpga"; - arm,vexpress-sysreg,func = <7 0>; - }; - -- shutdown@0 { +- shutdown at 0 { - compatible = "arm,vexpress-shutdown"; - arm,vexpress-sysreg,func = <8 0>; - }; - -- reboot@0 { +- reboot at 0 { - compatible = "arm,vexpress-reboot"; - arm,vexpress-sysreg,func = <9 0>; - }; - -- dvimode@0 { +- dvimode at 0 { - compatible = "arm,vexpress-dvimode"; - arm,vexpress-sysreg,func = <11 0>; - }; diff --git a/a/content_digest b/N1/content_digest index b881bf3..2e7ed2f 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,17 +1,8 @@ "ref\01409899692-1455-1-git-send-email-rric@kernel.org\0" - "From\0Robert Richter <rric@kernel.org>\0" + "From\0rric@kernel.org (Robert Richter)\0" "Subject\0[PATCH 5/6] dts, arm64: Move dts files to vendor subdirs\0" "Date\0Fri, 5 Sep 2014 08:48:11 +0200\0" - "To\0Olof Johansson <olof@lixom.net>" - Rob Herring <robh+dt@kernel.org> - Mark Rutland <mark.rutland@arm.com> - Arnd Bergmann <arnd@arndb.de> - " Michal Marek <mmarek@suse.cz>\0" - "Cc\0linux-arm-kernel@lists.infradead.org" - devicetree@vger.kernel.org - linux-kbuild@vger.kernel.org - linux-kernel@vger.kernel.org - " Robert Richter <rrichter@cavium.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "From: Robert Richter <rrichter@cavium.com>\n" @@ -126,56 +117,56 @@ "-\t\t#address-cells = <2>;\n" "-\t\t#size-cells = <0>;\n" "-\n" - "-\t\tcpu@000 {\n" + "-\t\tcpu at 000 {\n" "-\t\t\tdevice_type = \"cpu\";\n" "-\t\t\tcompatible = \"apm,potenza\", \"arm,armv8\";\n" "-\t\t\treg = <0x0 0x000>;\n" "-\t\t\tenable-method = \"spin-table\";\n" "-\t\t\tcpu-release-addr = <0x1 0x0000fff8>;\n" "-\t\t};\n" - "-\t\tcpu@001 {\n" + "-\t\tcpu at 001 {\n" "-\t\t\tdevice_type = \"cpu\";\n" "-\t\t\tcompatible = \"apm,potenza\", \"arm,armv8\";\n" "-\t\t\treg = <0x0 0x001>;\n" "-\t\t\tenable-method = \"spin-table\";\n" "-\t\t\tcpu-release-addr = <0x1 0x0000fff8>;\n" "-\t\t};\n" - "-\t\tcpu@100 {\n" + "-\t\tcpu at 100 {\n" "-\t\t\tdevice_type = \"cpu\";\n" "-\t\t\tcompatible = \"apm,potenza\", \"arm,armv8\";\n" "-\t\t\treg = <0x0 0x100>;\n" "-\t\t\tenable-method = \"spin-table\";\n" "-\t\t\tcpu-release-addr = <0x1 0x0000fff8>;\n" "-\t\t};\n" - "-\t\tcpu@101 {\n" + "-\t\tcpu at 101 {\n" "-\t\t\tdevice_type = \"cpu\";\n" "-\t\t\tcompatible = \"apm,potenza\", \"arm,armv8\";\n" "-\t\t\treg = <0x0 0x101>;\n" "-\t\t\tenable-method = \"spin-table\";\n" "-\t\t\tcpu-release-addr = <0x1 0x0000fff8>;\n" "-\t\t};\n" - "-\t\tcpu@200 {\n" + "-\t\tcpu at 200 {\n" "-\t\t\tdevice_type = \"cpu\";\n" "-\t\t\tcompatible = \"apm,potenza\", \"arm,armv8\";\n" "-\t\t\treg = <0x0 0x200>;\n" "-\t\t\tenable-method = \"spin-table\";\n" "-\t\t\tcpu-release-addr = <0x1 0x0000fff8>;\n" "-\t\t};\n" - "-\t\tcpu@201 {\n" + "-\t\tcpu at 201 {\n" "-\t\t\tdevice_type = \"cpu\";\n" "-\t\t\tcompatible = \"apm,potenza\", \"arm,armv8\";\n" "-\t\t\treg = <0x0 0x201>;\n" "-\t\t\tenable-method = \"spin-table\";\n" "-\t\t\tcpu-release-addr = <0x1 0x0000fff8>;\n" "-\t\t};\n" - "-\t\tcpu@300 {\n" + "-\t\tcpu at 300 {\n" "-\t\t\tdevice_type = \"cpu\";\n" "-\t\t\tcompatible = \"apm,potenza\", \"arm,armv8\";\n" "-\t\t\treg = <0x0 0x300>;\n" "-\t\t\tenable-method = \"spin-table\";\n" "-\t\t\tcpu-release-addr = <0x1 0x0000fff8>;\n" "-\t\t};\n" - "-\t\tcpu@301 {\n" + "-\t\tcpu at 301 {\n" "-\t\t\tdevice_type = \"cpu\";\n" "-\t\t\tcompatible = \"apm,potenza\", \"arm,armv8\";\n" "-\t\t\treg = <0x0 0x301>;\n" @@ -184,7 +175,7 @@ "-\t\t};\n" "-\t};\n" "-\n" - "-\tgic: interrupt-controller@78010000 {\n" + "-\tgic: interrupt-controller at 78010000 {\n" "-\t\tcompatible = \"arm,cortex-a15-gic\";\n" "-\t\t#interrupt-cells = <3>;\n" "-\t\tinterrupt-controller;\n" @@ -221,7 +212,7 @@ "-\t\t\t\tclock-output-names = \"refclk\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\tpcppll: pcppll@17000100 {\n" + "-\t\t\tpcppll: pcppll at 17000100 {\n" "-\t\t\t\tcompatible = \"apm,xgene-pcppll-clock\";\n" "-\t\t\t\t#clock-cells = <1>;\n" "-\t\t\t\tclocks = <&refclk 0>;\n" @@ -231,7 +222,7 @@ "-\t\t\t\ttype = <0>;\n" "-\t\t\t};\n" "-\n" - "-\t\t\tsocpll: socpll@17000120 {\n" + "-\t\t\tsocpll: socpll at 17000120 {\n" "-\t\t\t\tcompatible = \"apm,xgene-socpll-clock\";\n" "-\t\t\t\t#clock-cells = <1>;\n" "-\t\t\t\tclocks = <&refclk 0>;\n" @@ -283,7 +274,7 @@ "-\t\t\t\tclock-output-names = \"menetclk\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\tsataphy1clk: sataphy1clk@1f21c000 {\n" + "-\t\t\tsataphy1clk: sataphy1clk at 1f21c000 {\n" "-\t\t\t\tcompatible = \"apm,xgene-device-clock\";\n" "-\t\t\t\t#clock-cells = <1>;\n" "-\t\t\t\tclocks = <&socplldiv2 0>;\n" @@ -297,7 +288,7 @@ "-\t\t\t\tenable-mask = <0x06>;\n" "-\t\t\t};\n" "-\n" - "-\t\t\tsataphy2clk: sataphy1clk@1f22c000 {\n" + "-\t\t\tsataphy2clk: sataphy1clk at 1f22c000 {\n" "-\t\t\t\tcompatible = \"apm,xgene-device-clock\";\n" "-\t\t\t\t#clock-cells = <1>;\n" "-\t\t\t\tclocks = <&socplldiv2 0>;\n" @@ -311,7 +302,7 @@ "-\t\t\t\tenable-mask = <0x06>;\n" "-\t\t\t};\n" "-\n" - "-\t\t\tsataphy3clk: sataphy1clk@1f23c000 {\n" + "-\t\t\tsataphy3clk: sataphy1clk at 1f23c000 {\n" "-\t\t\t\tcompatible = \"apm,xgene-device-clock\";\n" "-\t\t\t\t#clock-cells = <1>;\n" "-\t\t\t\tclocks = <&socplldiv2 0>;\n" @@ -325,7 +316,7 @@ "-\t\t\t\tenable-mask = <0x06>;\n" "-\t\t\t};\n" "-\n" - "-\t\t\tsata01clk: sata01clk@1f21c000 {\n" + "-\t\t\tsata01clk: sata01clk at 1f21c000 {\n" "-\t\t\t\tcompatible = \"apm,xgene-device-clock\";\n" "-\t\t\t\t#clock-cells = <1>;\n" "-\t\t\t\tclocks = <&socplldiv2 0>;\n" @@ -338,7 +329,7 @@ "-\t\t\t\tenable-mask = <0x39>;\n" "-\t\t\t};\n" "-\n" - "-\t\t\tsata23clk: sata23clk@1f22c000 {\n" + "-\t\t\tsata23clk: sata23clk at 1f22c000 {\n" "-\t\t\t\tcompatible = \"apm,xgene-device-clock\";\n" "-\t\t\t\t#clock-cells = <1>;\n" "-\t\t\t\tclocks = <&socplldiv2 0>;\n" @@ -351,7 +342,7 @@ "-\t\t\t\tenable-mask = <0x39>;\n" "-\t\t\t};\n" "-\n" - "-\t\t\tsata45clk: sata45clk@1f23c000 {\n" + "-\t\t\tsata45clk: sata45clk at 1f23c000 {\n" "-\t\t\t\tcompatible = \"apm,xgene-device-clock\";\n" "-\t\t\t\t#clock-cells = <1>;\n" "-\t\t\t\tclocks = <&socplldiv2 0>;\n" @@ -364,7 +355,7 @@ "-\t\t\t\tenable-mask = <0x39>;\n" "-\t\t\t};\n" "-\n" - "-\t\t\trtcclk: rtcclk@17000000 {\n" + "-\t\t\trtcclk: rtcclk at 17000000 {\n" "-\t\t\t\tcompatible = \"apm,xgene-device-clock\";\n" "-\t\t\t\t#clock-cells = <1>;\n" "-\t\t\t\tclocks = <&socplldiv2 0>;\n" @@ -378,7 +369,7 @@ "-\t\t\t};\n" "-\t\t};\n" "-\n" - "-\t\tserial0: serial@1c020000 {\n" + "-\t\tserial0: serial at 1c020000 {\n" "-\t\t\tstatus = \"disabled\";\n" "-\t\t\tdevice_type = \"serial\";\n" "-\t\t\tcompatible = \"ns16550a\";\n" @@ -389,7 +380,7 @@ "-\t\t\tinterrupts = <0x0 0x4c 0x4>;\n" "-\t\t};\n" "-\n" - "-\t\tserial1: serial@1c021000 {\n" + "-\t\tserial1: serial at 1c021000 {\n" "-\t\t\tstatus = \"disabled\";\n" "-\t\t\tdevice_type = \"serial\";\n" "-\t\t\tcompatible = \"ns16550a\";\n" @@ -400,7 +391,7 @@ "-\t\t\tinterrupts = <0x0 0x4d 0x4>;\n" "-\t\t};\n" "-\n" - "-\t\tserial2: serial@1c022000 {\n" + "-\t\tserial2: serial at 1c022000 {\n" "-\t\t\tstatus = \"disabled\";\n" "-\t\t\tdevice_type = \"serial\";\n" "-\t\t\tcompatible = \"ns16550a\";\n" @@ -411,7 +402,7 @@ "-\t\t\tinterrupts = <0x0 0x4e 0x4>;\n" "-\t\t};\n" "-\n" - "-\t\tserial3: serial@1c023000 {\n" + "-\t\tserial3: serial at 1c023000 {\n" "-\t\t\tstatus = \"disabled\";\n" "-\t\t\tdevice_type = \"serial\";\n" "-\t\t\tcompatible = \"ns16550a\";\n" @@ -422,7 +413,7 @@ "-\t\t\tinterrupts = <0x0 0x4f 0x4>;\n" "-\t\t};\n" "-\n" - "-\t\tphy1: phy@1f21a000 {\n" + "-\t\tphy1: phy at 1f21a000 {\n" "-\t\t\tcompatible = \"apm,xgene-phy\";\n" "-\t\t\treg = <0x0 0x1f21a000 0x0 0x100>;\n" "-\t\t\t#phy-cells = <1>;\n" @@ -432,7 +423,7 @@ "-\t\t\tapm,tx-eye-tuning = <2 10 10 2 10 10>;\n" "-\t\t};\n" "-\n" - "-\t\tphy2: phy@1f22a000 {\n" + "-\t\tphy2: phy at 1f22a000 {\n" "-\t\t\tcompatible = \"apm,xgene-phy\";\n" "-\t\t\treg = <0x0 0x1f22a000 0x0 0x100>;\n" "-\t\t\t#phy-cells = <1>;\n" @@ -442,7 +433,7 @@ "-\t\t\tapm,tx-eye-tuning = <1 10 10 2 10 10>;\n" "-\t\t};\n" "-\n" - "-\t\tphy3: phy@1f23a000 {\n" + "-\t\tphy3: phy at 1f23a000 {\n" "-\t\t\tcompatible = \"apm,xgene-phy\";\n" "-\t\t\treg = <0x0 0x1f23a000 0x0 0x100>;\n" "-\t\t\t#phy-cells = <1>;\n" @@ -452,7 +443,7 @@ "-\t\t\tapm,tx-eye-tuning = <2 10 10 2 10 10>;\n" "-\t\t};\n" "-\n" - "-\t\tsata1: sata@1a000000 {\n" + "-\t\tsata1: sata at 1a000000 {\n" "-\t\t\tcompatible = \"apm,xgene-ahci\";\n" "-\t\t\treg = <0x0 0x1a000000 0x0 0x1000>,\n" "-\t\t\t <0x0 0x1f210000 0x0 0x1000>,\n" @@ -467,7 +458,7 @@ "-\t\t\tphy-names = \"sata-phy\";\n" "-\t\t};\n" "-\n" - "-\t\tsata2: sata@1a400000 {\n" + "-\t\tsata2: sata at 1a400000 {\n" "-\t\t\tcompatible = \"apm,xgene-ahci\";\n" "-\t\t\treg = <0x0 0x1a400000 0x0 0x1000>,\n" "-\t\t\t <0x0 0x1f220000 0x0 0x1000>,\n" @@ -482,7 +473,7 @@ "-\t\t\tphy-names = \"sata-phy\";\n" "-\t\t};\n" "-\n" - "-\t\tsata3: sata@1a800000 {\n" + "-\t\tsata3: sata at 1a800000 {\n" "-\t\t\tcompatible = \"apm,xgene-ahci\";\n" "-\t\t\treg = <0x0 0x1a800000 0x0 0x1000>,\n" "-\t\t\t <0x0 0x1f230000 0x0 0x1000>,\n" @@ -496,7 +487,7 @@ "-\t\t\tphy-names = \"sata-phy\";\n" "-\t\t};\n" "-\n" - "-\t\trtc: rtc@10510000 {\n" + "-\t\trtc: rtc at 10510000 {\n" "-\t\t\tcompatible = \"apm,xgene-rtc\";\n" "-\t\t\treg = <0x0 0x10510000 0x0 0x400>;\n" "-\t\t\tinterrupts = <0x0 0x46 0x4>;\n" @@ -504,7 +495,7 @@ "-\t\t\tclocks = <&rtcclk 0>;\n" "-\t\t};\n" "-\n" - "-\t\tmenet: ethernet@17020000 {\n" + "-\t\tmenet: ethernet at 17020000 {\n" "-\t\t\tcompatible = \"apm,xgene-enet\";\n" "-\t\t\tstatus = \"disabled\";\n" "-\t\t\treg = <0x0 0x17020000 0x0 0xd100>,\n" @@ -521,7 +512,7 @@ "-\t\t\t\tcompatible = \"apm,xgene-mdio\";\n" "-\t\t\t\t#address-cells = <1>;\n" "-\t\t\t\t#size-cells = <0>;\n" - "-\t\t\t\tmenetphy: menetphy@3 {\n" + "-\t\t\t\tmenetphy: menetphy at 3 {\n" "-\t\t\t\t\tcompatible = \"ethernet-phy-id001c.c915\";\n" "-\t\t\t\t\treg = <0x3>;\n" "-\t\t\t\t};\n" @@ -608,56 +599,56 @@ "+\t\t#address-cells = <2>;\n" "+\t\t#size-cells = <0>;\n" "+\n" - "+\t\tcpu@000 {\n" + "+\t\tcpu at 000 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"apm,potenza\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x000>;\n" "+\t\t\tenable-method = \"spin-table\";\n" "+\t\t\tcpu-release-addr = <0x1 0x0000fff8>;\n" "+\t\t};\n" - "+\t\tcpu@001 {\n" + "+\t\tcpu at 001 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"apm,potenza\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x001>;\n" "+\t\t\tenable-method = \"spin-table\";\n" "+\t\t\tcpu-release-addr = <0x1 0x0000fff8>;\n" "+\t\t};\n" - "+\t\tcpu@100 {\n" + "+\t\tcpu at 100 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"apm,potenza\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x100>;\n" "+\t\t\tenable-method = \"spin-table\";\n" "+\t\t\tcpu-release-addr = <0x1 0x0000fff8>;\n" "+\t\t};\n" - "+\t\tcpu@101 {\n" + "+\t\tcpu at 101 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"apm,potenza\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x101>;\n" "+\t\t\tenable-method = \"spin-table\";\n" "+\t\t\tcpu-release-addr = <0x1 0x0000fff8>;\n" "+\t\t};\n" - "+\t\tcpu@200 {\n" + "+\t\tcpu at 200 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"apm,potenza\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x200>;\n" "+\t\t\tenable-method = \"spin-table\";\n" "+\t\t\tcpu-release-addr = <0x1 0x0000fff8>;\n" "+\t\t};\n" - "+\t\tcpu@201 {\n" + "+\t\tcpu at 201 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"apm,potenza\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x201>;\n" "+\t\t\tenable-method = \"spin-table\";\n" "+\t\t\tcpu-release-addr = <0x1 0x0000fff8>;\n" "+\t\t};\n" - "+\t\tcpu@300 {\n" + "+\t\tcpu at 300 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"apm,potenza\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x300>;\n" "+\t\t\tenable-method = \"spin-table\";\n" "+\t\t\tcpu-release-addr = <0x1 0x0000fff8>;\n" "+\t\t};\n" - "+\t\tcpu@301 {\n" + "+\t\tcpu at 301 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"apm,potenza\", \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x301>;\n" @@ -666,7 +657,7 @@ "+\t\t};\n" "+\t};\n" "+\n" - "+\tgic: interrupt-controller@78010000 {\n" + "+\tgic: interrupt-controller at 78010000 {\n" "+\t\tcompatible = \"arm,cortex-a15-gic\";\n" "+\t\t#interrupt-cells = <3>;\n" "+\t\tinterrupt-controller;\n" @@ -703,7 +694,7 @@ "+\t\t\t\tclock-output-names = \"refclk\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tpcppll: pcppll@17000100 {\n" + "+\t\t\tpcppll: pcppll at 17000100 {\n" "+\t\t\t\tcompatible = \"apm,xgene-pcppll-clock\";\n" "+\t\t\t\t#clock-cells = <1>;\n" "+\t\t\t\tclocks = <&refclk 0>;\n" @@ -713,7 +704,7 @@ "+\t\t\t\ttype = <0>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tsocpll: socpll@17000120 {\n" + "+\t\t\tsocpll: socpll at 17000120 {\n" "+\t\t\t\tcompatible = \"apm,xgene-socpll-clock\";\n" "+\t\t\t\t#clock-cells = <1>;\n" "+\t\t\t\tclocks = <&refclk 0>;\n" @@ -765,7 +756,7 @@ "+\t\t\t\tclock-output-names = \"menetclk\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tsataphy1clk: sataphy1clk@1f21c000 {\n" + "+\t\t\tsataphy1clk: sataphy1clk at 1f21c000 {\n" "+\t\t\t\tcompatible = \"apm,xgene-device-clock\";\n" "+\t\t\t\t#clock-cells = <1>;\n" "+\t\t\t\tclocks = <&socplldiv2 0>;\n" @@ -779,7 +770,7 @@ "+\t\t\t\tenable-mask = <0x06>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tsataphy2clk: sataphy1clk@1f22c000 {\n" + "+\t\t\tsataphy2clk: sataphy1clk at 1f22c000 {\n" "+\t\t\t\tcompatible = \"apm,xgene-device-clock\";\n" "+\t\t\t\t#clock-cells = <1>;\n" "+\t\t\t\tclocks = <&socplldiv2 0>;\n" @@ -793,7 +784,7 @@ "+\t\t\t\tenable-mask = <0x06>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tsataphy3clk: sataphy1clk@1f23c000 {\n" + "+\t\t\tsataphy3clk: sataphy1clk at 1f23c000 {\n" "+\t\t\t\tcompatible = \"apm,xgene-device-clock\";\n" "+\t\t\t\t#clock-cells = <1>;\n" "+\t\t\t\tclocks = <&socplldiv2 0>;\n" @@ -807,7 +798,7 @@ "+\t\t\t\tenable-mask = <0x06>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tsata01clk: sata01clk@1f21c000 {\n" + "+\t\t\tsata01clk: sata01clk at 1f21c000 {\n" "+\t\t\t\tcompatible = \"apm,xgene-device-clock\";\n" "+\t\t\t\t#clock-cells = <1>;\n" "+\t\t\t\tclocks = <&socplldiv2 0>;\n" @@ -820,7 +811,7 @@ "+\t\t\t\tenable-mask = <0x39>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tsata23clk: sata23clk@1f22c000 {\n" + "+\t\t\tsata23clk: sata23clk at 1f22c000 {\n" "+\t\t\t\tcompatible = \"apm,xgene-device-clock\";\n" "+\t\t\t\t#clock-cells = <1>;\n" "+\t\t\t\tclocks = <&socplldiv2 0>;\n" @@ -833,7 +824,7 @@ "+\t\t\t\tenable-mask = <0x39>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tsata45clk: sata45clk@1f23c000 {\n" + "+\t\t\tsata45clk: sata45clk at 1f23c000 {\n" "+\t\t\t\tcompatible = \"apm,xgene-device-clock\";\n" "+\t\t\t\t#clock-cells = <1>;\n" "+\t\t\t\tclocks = <&socplldiv2 0>;\n" @@ -846,7 +837,7 @@ "+\t\t\t\tenable-mask = <0x39>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\trtcclk: rtcclk@17000000 {\n" + "+\t\t\trtcclk: rtcclk at 17000000 {\n" "+\t\t\t\tcompatible = \"apm,xgene-device-clock\";\n" "+\t\t\t\t#clock-cells = <1>;\n" "+\t\t\t\tclocks = <&socplldiv2 0>;\n" @@ -860,7 +851,7 @@ "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tserial0: serial@1c020000 {\n" + "+\t\tserial0: serial at 1c020000 {\n" "+\t\t\tstatus = \"disabled\";\n" "+\t\t\tdevice_type = \"serial\";\n" "+\t\t\tcompatible = \"ns16550a\";\n" @@ -871,7 +862,7 @@ "+\t\t\tinterrupts = <0x0 0x4c 0x4>;\n" "+\t\t};\n" "+\n" - "+\t\tserial1: serial@1c021000 {\n" + "+\t\tserial1: serial at 1c021000 {\n" "+\t\t\tstatus = \"disabled\";\n" "+\t\t\tdevice_type = \"serial\";\n" "+\t\t\tcompatible = \"ns16550a\";\n" @@ -882,7 +873,7 @@ "+\t\t\tinterrupts = <0x0 0x4d 0x4>;\n" "+\t\t};\n" "+\n" - "+\t\tserial2: serial@1c022000 {\n" + "+\t\tserial2: serial at 1c022000 {\n" "+\t\t\tstatus = \"disabled\";\n" "+\t\t\tdevice_type = \"serial\";\n" "+\t\t\tcompatible = \"ns16550a\";\n" @@ -893,7 +884,7 @@ "+\t\t\tinterrupts = <0x0 0x4e 0x4>;\n" "+\t\t};\n" "+\n" - "+\t\tserial3: serial@1c023000 {\n" + "+\t\tserial3: serial at 1c023000 {\n" "+\t\t\tstatus = \"disabled\";\n" "+\t\t\tdevice_type = \"serial\";\n" "+\t\t\tcompatible = \"ns16550a\";\n" @@ -904,7 +895,7 @@ "+\t\t\tinterrupts = <0x0 0x4f 0x4>;\n" "+\t\t};\n" "+\n" - "+\t\tphy1: phy@1f21a000 {\n" + "+\t\tphy1: phy at 1f21a000 {\n" "+\t\t\tcompatible = \"apm,xgene-phy\";\n" "+\t\t\treg = <0x0 0x1f21a000 0x0 0x100>;\n" "+\t\t\t#phy-cells = <1>;\n" @@ -914,7 +905,7 @@ "+\t\t\tapm,tx-eye-tuning = <2 10 10 2 10 10>;\n" "+\t\t};\n" "+\n" - "+\t\tphy2: phy@1f22a000 {\n" + "+\t\tphy2: phy at 1f22a000 {\n" "+\t\t\tcompatible = \"apm,xgene-phy\";\n" "+\t\t\treg = <0x0 0x1f22a000 0x0 0x100>;\n" "+\t\t\t#phy-cells = <1>;\n" @@ -924,7 +915,7 @@ "+\t\t\tapm,tx-eye-tuning = <1 10 10 2 10 10>;\n" "+\t\t};\n" "+\n" - "+\t\tphy3: phy@1f23a000 {\n" + "+\t\tphy3: phy at 1f23a000 {\n" "+\t\t\tcompatible = \"apm,xgene-phy\";\n" "+\t\t\treg = <0x0 0x1f23a000 0x0 0x100>;\n" "+\t\t\t#phy-cells = <1>;\n" @@ -934,7 +925,7 @@ "+\t\t\tapm,tx-eye-tuning = <2 10 10 2 10 10>;\n" "+\t\t};\n" "+\n" - "+\t\tsata1: sata@1a000000 {\n" + "+\t\tsata1: sata at 1a000000 {\n" "+\t\t\tcompatible = \"apm,xgene-ahci\";\n" "+\t\t\treg = <0x0 0x1a000000 0x0 0x1000>,\n" "+\t\t\t <0x0 0x1f210000 0x0 0x1000>,\n" @@ -949,7 +940,7 @@ "+\t\t\tphy-names = \"sata-phy\";\n" "+\t\t};\n" "+\n" - "+\t\tsata2: sata@1a400000 {\n" + "+\t\tsata2: sata at 1a400000 {\n" "+\t\t\tcompatible = \"apm,xgene-ahci\";\n" "+\t\t\treg = <0x0 0x1a400000 0x0 0x1000>,\n" "+\t\t\t <0x0 0x1f220000 0x0 0x1000>,\n" @@ -964,7 +955,7 @@ "+\t\t\tphy-names = \"sata-phy\";\n" "+\t\t};\n" "+\n" - "+\t\tsata3: sata@1a800000 {\n" + "+\t\tsata3: sata at 1a800000 {\n" "+\t\t\tcompatible = \"apm,xgene-ahci\";\n" "+\t\t\treg = <0x0 0x1a800000 0x0 0x1000>,\n" "+\t\t\t <0x0 0x1f230000 0x0 0x1000>,\n" @@ -978,7 +969,7 @@ "+\t\t\tphy-names = \"sata-phy\";\n" "+\t\t};\n" "+\n" - "+\t\trtc: rtc@10510000 {\n" + "+\t\trtc: rtc at 10510000 {\n" "+\t\t\tcompatible = \"apm,xgene-rtc\";\n" "+\t\t\treg = <0x0 0x10510000 0x0 0x400>;\n" "+\t\t\tinterrupts = <0x0 0x46 0x4>;\n" @@ -986,7 +977,7 @@ "+\t\t\tclocks = <&rtcclk 0>;\n" "+\t\t};\n" "+\n" - "+\t\tmenet: ethernet@17020000 {\n" + "+\t\tmenet: ethernet at 17020000 {\n" "+\t\t\tcompatible = \"apm,xgene-enet\";\n" "+\t\t\tstatus = \"disabled\";\n" "+\t\t\treg = <0x0 0x17020000 0x0 0xd100>,\n" @@ -1003,7 +994,7 @@ "+\t\t\t\tcompatible = \"apm,xgene-mdio\";\n" "+\t\t\t\t#address-cells = <1>;\n" "+\t\t\t\t#size-cells = <0>;\n" - "+\t\t\t\tmenetphy: menetphy@3 {\n" + "+\t\t\t\tmenetphy: menetphy at 3 {\n" "+\t\t\t\t\tcompatible = \"ethernet-phy-id001c.c915\";\n" "+\t\t\t\t\treg = <0x3>;\n" "+\t\t\t\t};\n" @@ -1060,28 +1051,28 @@ "+\t\t#address-cells = <2>;\n" "+\t\t#size-cells = <0>;\n" "+\n" - "+\t\tcpu@0 {\n" + "+\t\tcpu at 0 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x0>;\n" "+\t\t\tenable-method = \"spin-table\";\n" "+\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "+\t\t};\n" - "+\t\tcpu@1 {\n" + "+\t\tcpu at 1 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x1>;\n" "+\t\t\tenable-method = \"spin-table\";\n" "+\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "+\t\t};\n" - "+\t\tcpu@2 {\n" + "+\t\tcpu at 2 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x2>;\n" "+\t\t\tenable-method = \"spin-table\";\n" "+\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "+\t\t};\n" - "+\t\tcpu@3 {\n" + "+\t\tcpu at 3 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x3>;\n" @@ -1090,13 +1081,13 @@ "+\t\t};\n" "+\t};\n" "+\n" - "+\tmemory@80000000 {\n" + "+\tmemory at 80000000 {\n" "+\t\tdevice_type = \"memory\";\n" "+\t\treg = <0x00000000 0x80000000 0 0x80000000>,\n" "+\t\t <0x00000008 0x80000000 0 0x80000000>;\n" "+\t};\n" "+\n" - "+\tgic: interrupt-controller@2c001000 {\n" + "+\tgic: interrupt-controller at 2c001000 {\n" "+\t\tcompatible = \"arm,cortex-a15-gic\", \"arm,cortex-a9-gic\";\n" "+\t\t#interrupt-cells = <3>;\n" "+\t\t#address-cells = <0>;\n" @@ -1184,7 +1175,7 @@ "+\t\t\t\t<0 0 41 &gic 0 41 4>,\n" "+\t\t\t\t<0 0 42 &gic 0 42 4>;\n" "+\n" - "+\t\tethernet@2,02000000 {\n" + "+\t\tethernet at 2,02000000 {\n" "+\t\t\tcompatible = \"smsc,lan91c111\";\n" "+\t\t\treg = <2 0x02000000 0x10000>;\n" "+\t\t\tinterrupts = <15>;\n" @@ -1211,18 +1202,18 @@ "+\t\t\tclock-output-names = \"v2m:refclk32khz\";\n" "+\t\t};\n" "+\n" - "+\t\tiofpga@3,00000000 {\n" + "+\t\tiofpga at 3,00000000 {\n" "+\t\t\tcompatible = \"arm,amba-bus\", \"simple-bus\";\n" "+\t\t\t#address-cells = <1>;\n" "+\t\t\t#size-cells = <1>;\n" "+\t\t\tranges = <0 3 0 0x200000>;\n" "+\n" - "+\t\t\tv2m_sysreg: sysreg@010000 {\n" + "+\t\t\tv2m_sysreg: sysreg at 010000 {\n" "+\t\t\t\tcompatible = \"arm,vexpress-sysreg\";\n" "+\t\t\t\treg = <0x010000 0x1000>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tv2m_serial0: uart@090000 {\n" + "+\t\t\tv2m_serial0: uart at 090000 {\n" "+\t\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "+\t\t\t\treg = <0x090000 0x1000>;\n" "+\t\t\t\tinterrupts = <5>;\n" @@ -1230,7 +1221,7 @@ "+\t\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tv2m_serial1: uart@0a0000 {\n" + "+\t\t\tv2m_serial1: uart at 0a0000 {\n" "+\t\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "+\t\t\t\treg = <0x0a0000 0x1000>;\n" "+\t\t\t\tinterrupts = <6>;\n" @@ -1238,7 +1229,7 @@ "+\t\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tv2m_serial2: uart@0b0000 {\n" + "+\t\t\tv2m_serial2: uart at 0b0000 {\n" "+\t\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "+\t\t\t\treg = <0x0b0000 0x1000>;\n" "+\t\t\t\tinterrupts = <7>;\n" @@ -1246,7 +1237,7 @@ "+\t\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tv2m_serial3: uart@0c0000 {\n" + "+\t\t\tv2m_serial3: uart at 0c0000 {\n" "+\t\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "+\t\t\t\treg = <0x0c0000 0x1000>;\n" "+\t\t\t\tinterrupts = <8>;\n" @@ -1254,7 +1245,7 @@ "+\t\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tvirtio_block@0130000 {\n" + "+\t\t\tvirtio_block at 0130000 {\n" "+\t\t\t\tcompatible = \"virtio,mmio\";\n" "+\t\t\t\treg = <0x130000 0x200>;\n" "+\t\t\t\tinterrupts = <42>;\n" @@ -1301,28 +1292,28 @@ "+\t\t#address-cells = <2>;\n" "+\t\t#size-cells = <0>;\n" "+\n" - "+\t\tcpu@0 {\n" + "+\t\tcpu at 0 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x0>;\n" "+\t\t\tenable-method = \"spin-table\";\n" "+\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "+\t\t};\n" - "+\t\tcpu@1 {\n" + "+\t\tcpu at 1 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x1>;\n" "+\t\t\tenable-method = \"spin-table\";\n" "+\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "+\t\t};\n" - "+\t\tcpu@2 {\n" + "+\t\tcpu at 2 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x2>;\n" "+\t\t\tenable-method = \"spin-table\";\n" "+\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "+\t\t};\n" - "+\t\tcpu@3 {\n" + "+\t\tcpu at 3 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,armv8\";\n" "+\t\t\treg = <0x0 0x3>;\n" @@ -1331,13 +1322,13 @@ "+\t\t};\n" "+\t};\n" "+\n" - "+\tmemory@80000000 {\n" + "+\tmemory at 80000000 {\n" "+\t\tdevice_type = \"memory\";\n" "+\t\treg = <0x00000000 0x80000000 0 0x80000000>,\n" "+\t\t <0x00000008 0x80000000 0 0x80000000>;\n" "+\t};\n" "+\n" - "+\tgic: interrupt-controller@2c001000 {\n" + "+\tgic: interrupt-controller at 2c001000 {\n" "+\t\tcompatible = \"arm,cortex-a15-gic\", \"arm,cortex-a9-gic\";\n" "+\t\t#interrupt-cells = <3>;\n" "+\t\t#address-cells = <0>;\n" @@ -1450,19 +1441,19 @@ "+\t\t#interrupt-cells = <1>;\n" "+\t\tranges;\n" "+\n" - "+\t\tflash@0,00000000 {\n" + "+\t\tflash at 0,00000000 {\n" "+\t\t\tcompatible = \"arm,vexpress-flash\", \"cfi-flash\";\n" "+\t\t\treg = <0 0x00000000 0x04000000>,\n" "+\t\t\t <4 0x00000000 0x04000000>;\n" "+\t\t\tbank-width = <4>;\n" "+\t\t};\n" "+\n" - "+\t\tvram@2,00000000 {\n" + "+\t\tvram at 2,00000000 {\n" "+\t\t\tcompatible = \"arm,vexpress-vram\";\n" "+\t\t\treg = <2 0x00000000 0x00800000>;\n" "+\t\t};\n" "+\n" - "+\t\tethernet@2,02000000 {\n" + "+\t\tethernet at 2,02000000 {\n" "+\t\t\tcompatible = \"smsc,lan91c111\";\n" "+\t\t\treg = <2 0x02000000 0x10000>;\n" "+\t\t\tinterrupts = <15>;\n" @@ -1489,20 +1480,20 @@ "+\t\t\tclock-output-names = \"v2m:refclk32khz\";\n" "+\t\t};\n" "+\n" - "+\t\tiofpga@3,00000000 {\n" + "+\t\tiofpga at 3,00000000 {\n" "+\t\t\tcompatible = \"arm,amba-bus\", \"simple-bus\";\n" "+\t\t\t#address-cells = <1>;\n" "+\t\t\t#size-cells = <1>;\n" "+\t\t\tranges = <0 3 0 0x200000>;\n" "+\n" - "+\t\t\tv2m_sysreg: sysreg@010000 {\n" + "+\t\t\tv2m_sysreg: sysreg at 010000 {\n" "+\t\t\t\tcompatible = \"arm,vexpress-sysreg\";\n" "+\t\t\t\treg = <0x010000 0x1000>;\n" "+\t\t\t\tgpio-controller;\n" "+\t\t\t\t#gpio-cells = <2>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tv2m_sysctl: sysctl@020000 {\n" + "+\t\t\tv2m_sysctl: sysctl at 020000 {\n" "+\t\t\t\tcompatible = \"arm,sp810\", \"arm,primecell\";\n" "+\t\t\t\treg = <0x020000 0x1000>;\n" "+\t\t\t\tclocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;\n" @@ -1511,7 +1502,7 @@ "+\t\t\t\tclock-output-names = \"timerclken0\", \"timerclken1\", \"timerclken2\", \"timerclken3\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\taaci@040000 {\n" + "+\t\t\taaci at 040000 {\n" "+\t\t\t\tcompatible = \"arm,pl041\", \"arm,primecell\";\n" "+\t\t\t\treg = <0x040000 0x1000>;\n" "+\t\t\t\tinterrupts = <11>;\n" @@ -1519,7 +1510,7 @@ "+\t\t\t\tclock-names = \"apb_pclk\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tmmci@050000 {\n" + "+\t\t\tmmci at 050000 {\n" "+\t\t\t\tcompatible = \"arm,pl180\", \"arm,primecell\";\n" "+\t\t\t\treg = <0x050000 0x1000>;\n" "+\t\t\t\tinterrupts = <9 10>;\n" @@ -1531,7 +1522,7 @@ "+\t\t\t\tclock-names = \"mclk\", \"apb_pclk\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tkmi@060000 {\n" + "+\t\t\tkmi at 060000 {\n" "+\t\t\t\tcompatible = \"arm,pl050\", \"arm,primecell\";\n" "+\t\t\t\treg = <0x060000 0x1000>;\n" "+\t\t\t\tinterrupts = <12>;\n" @@ -1539,7 +1530,7 @@ "+\t\t\t\tclock-names = \"KMIREFCLK\", \"apb_pclk\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tkmi@070000 {\n" + "+\t\t\tkmi at 070000 {\n" "+\t\t\t\tcompatible = \"arm,pl050\", \"arm,primecell\";\n" "+\t\t\t\treg = <0x070000 0x1000>;\n" "+\t\t\t\tinterrupts = <13>;\n" @@ -1547,7 +1538,7 @@ "+\t\t\t\tclock-names = \"KMIREFCLK\", \"apb_pclk\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tv2m_serial0: uart@090000 {\n" + "+\t\t\tv2m_serial0: uart at 090000 {\n" "+\t\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "+\t\t\t\treg = <0x090000 0x1000>;\n" "+\t\t\t\tinterrupts = <5>;\n" @@ -1555,7 +1546,7 @@ "+\t\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tv2m_serial1: uart@0a0000 {\n" + "+\t\t\tv2m_serial1: uart at 0a0000 {\n" "+\t\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "+\t\t\t\treg = <0x0a0000 0x1000>;\n" "+\t\t\t\tinterrupts = <6>;\n" @@ -1563,7 +1554,7 @@ "+\t\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tv2m_serial2: uart@0b0000 {\n" + "+\t\t\tv2m_serial2: uart at 0b0000 {\n" "+\t\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "+\t\t\t\treg = <0x0b0000 0x1000>;\n" "+\t\t\t\tinterrupts = <7>;\n" @@ -1571,7 +1562,7 @@ "+\t\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tv2m_serial3: uart@0c0000 {\n" + "+\t\t\tv2m_serial3: uart at 0c0000 {\n" "+\t\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "+\t\t\t\treg = <0x0c0000 0x1000>;\n" "+\t\t\t\tinterrupts = <8>;\n" @@ -1579,7 +1570,7 @@ "+\t\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\twdt@0f0000 {\n" + "+\t\t\twdt at 0f0000 {\n" "+\t\t\t\tcompatible = \"arm,sp805\", \"arm,primecell\";\n" "+\t\t\t\treg = <0x0f0000 0x1000>;\n" "+\t\t\t\tinterrupts = <0>;\n" @@ -1587,7 +1578,7 @@ "+\t\t\t\tclock-names = \"wdogclk\", \"apb_pclk\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tv2m_timer01: timer@110000 {\n" + "+\t\t\tv2m_timer01: timer at 110000 {\n" "+\t\t\t\tcompatible = \"arm,sp804\", \"arm,primecell\";\n" "+\t\t\t\treg = <0x110000 0x1000>;\n" "+\t\t\t\tinterrupts = <2>;\n" @@ -1595,7 +1586,7 @@ "+\t\t\t\tclock-names = \"timclken1\", \"timclken2\", \"apb_pclk\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tv2m_timer23: timer@120000 {\n" + "+\t\t\tv2m_timer23: timer at 120000 {\n" "+\t\t\t\tcompatible = \"arm,sp804\", \"arm,primecell\";\n" "+\t\t\t\treg = <0x120000 0x1000>;\n" "+\t\t\t\tinterrupts = <3>;\n" @@ -1603,7 +1594,7 @@ "+\t\t\t\tclock-names = \"timclken1\", \"timclken2\", \"apb_pclk\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\trtc@170000 {\n" + "+\t\t\trtc at 170000 {\n" "+\t\t\t\tcompatible = \"arm,pl031\", \"arm,primecell\";\n" "+\t\t\t\treg = <0x170000 0x1000>;\n" "+\t\t\t\tinterrupts = <4>;\n" @@ -1611,7 +1602,7 @@ "+\t\t\t\tclock-names = \"apb_pclk\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tclcd@1f0000 {\n" + "+\t\t\tclcd at 1f0000 {\n" "+\t\t\t\tcompatible = \"arm,pl111\", \"arm,primecell\";\n" "+\t\t\t\treg = <0x1f0000 0x1000>;\n" "+\t\t\t\tinterrupts = <14>;\n" @@ -1619,14 +1610,14 @@ "+\t\t\t\tclock-names = \"clcdclk\", \"apb_pclk\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tvirtio_block@0130000 {\n" + "+\t\t\tvirtio_block at 0130000 {\n" "+\t\t\t\tcompatible = \"virtio,mmio\";\n" "+\t\t\t\treg = <0x130000 0x200>;\n" "+\t\t\t\tinterrupts = <42>;\n" "+\t\t\t};\n" "+\t\t};\n" "+\n" - "+\t\tv2m_fixed_3v3: fixedregulator@0 {\n" + "+\t\tv2m_fixed_3v3: fixedregulator at 0 {\n" "+\t\t\tcompatible = \"regulator-fixed\";\n" "+\t\t\tregulator-name = \"3V3\";\n" "+\t\t\tregulator-min-microvolt = <3300000>;\n" @@ -1638,7 +1629,7 @@ "+\t\t\tcompatible = \"arm,vexpress,config-bus\";\n" "+\t\t\tarm,vexpress,config-bridge = <&v2m_sysreg>;\n" "+\n" - "+\t\t\tv2m_oscclk1: osc@1 {\n" + "+\t\t\tv2m_oscclk1: osc at 1 {\n" "+\t\t\t\t/* CLCD clock */\n" "+\t\t\t\tcompatible = \"arm,vexpress-osc\";\n" "+\t\t\t\tarm,vexpress-sysreg,func = <1 1>;\n" @@ -1647,27 +1638,27 @@ "+\t\t\t\tclock-output-names = \"v2m:oscclk1\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\treset@0 {\n" + "+\t\t\treset at 0 {\n" "+\t\t\t\tcompatible = \"arm,vexpress-reset\";\n" "+\t\t\t\tarm,vexpress-sysreg,func = <5 0>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tmuxfpga@0 {\n" + "+\t\t\tmuxfpga at 0 {\n" "+\t\t\t\tcompatible = \"arm,vexpress-muxfpga\";\n" "+\t\t\t\tarm,vexpress-sysreg,func = <7 0>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tshutdown@0 {\n" + "+\t\t\tshutdown at 0 {\n" "+\t\t\t\tcompatible = \"arm,vexpress-shutdown\";\n" "+\t\t\t\tarm,vexpress-sysreg,func = <8 0>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\treboot@0 {\n" + "+\t\t\treboot at 0 {\n" "+\t\t\t\tcompatible = \"arm,vexpress-reboot\";\n" "+\t\t\t\tarm,vexpress-sysreg,func = <9 0>;\n" "+\t\t\t};\n" "+\n" - "+\t\t\tdvimode@0 {\n" + "+\t\t\tdvimode at 0 {\n" "+\t\t\t\tcompatible = \"arm,vexpress-dvimode\";\n" "+\t\t\t\tarm,vexpress-sysreg,func = <11 0>;\n" "+\t\t\t};\n" @@ -1709,28 +1700,28 @@ "-\t\t#address-cells = <2>;\n" "-\t\t#size-cells = <0>;\n" "-\n" - "-\t\tcpu@0 {\n" + "-\t\tcpu at 0 {\n" "-\t\t\tdevice_type = \"cpu\";\n" "-\t\t\tcompatible = \"arm,armv8\";\n" "-\t\t\treg = <0x0 0x0>;\n" "-\t\t\tenable-method = \"spin-table\";\n" "-\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "-\t\t};\n" - "-\t\tcpu@1 {\n" + "-\t\tcpu at 1 {\n" "-\t\t\tdevice_type = \"cpu\";\n" "-\t\t\tcompatible = \"arm,armv8\";\n" "-\t\t\treg = <0x0 0x1>;\n" "-\t\t\tenable-method = \"spin-table\";\n" "-\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "-\t\t};\n" - "-\t\tcpu@2 {\n" + "-\t\tcpu at 2 {\n" "-\t\t\tdevice_type = \"cpu\";\n" "-\t\t\tcompatible = \"arm,armv8\";\n" "-\t\t\treg = <0x0 0x2>;\n" "-\t\t\tenable-method = \"spin-table\";\n" "-\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "-\t\t};\n" - "-\t\tcpu@3 {\n" + "-\t\tcpu at 3 {\n" "-\t\t\tdevice_type = \"cpu\";\n" "-\t\t\tcompatible = \"arm,armv8\";\n" "-\t\t\treg = <0x0 0x3>;\n" @@ -1739,13 +1730,13 @@ "-\t\t};\n" "-\t};\n" "-\n" - "-\tmemory@80000000 {\n" + "-\tmemory at 80000000 {\n" "-\t\tdevice_type = \"memory\";\n" "-\t\treg = <0x00000000 0x80000000 0 0x80000000>,\n" "-\t\t <0x00000008 0x80000000 0 0x80000000>;\n" "-\t};\n" "-\n" - "-\tgic: interrupt-controller@2c001000 {\n" + "-\tgic: interrupt-controller at 2c001000 {\n" "-\t\tcompatible = \"arm,cortex-a15-gic\", \"arm,cortex-a9-gic\";\n" "-\t\t#interrupt-cells = <3>;\n" "-\t\t#address-cells = <0>;\n" @@ -1833,7 +1824,7 @@ "-\t\t\t\t<0 0 41 &gic 0 41 4>,\n" "-\t\t\t\t<0 0 42 &gic 0 42 4>;\n" "-\n" - "-\t\tethernet@2,02000000 {\n" + "-\t\tethernet at 2,02000000 {\n" "-\t\t\tcompatible = \"smsc,lan91c111\";\n" "-\t\t\treg = <2 0x02000000 0x10000>;\n" "-\t\t\tinterrupts = <15>;\n" @@ -1860,18 +1851,18 @@ "-\t\t\tclock-output-names = \"v2m:refclk32khz\";\n" "-\t\t};\n" "-\n" - "-\t\tiofpga@3,00000000 {\n" + "-\t\tiofpga at 3,00000000 {\n" "-\t\t\tcompatible = \"arm,amba-bus\", \"simple-bus\";\n" "-\t\t\t#address-cells = <1>;\n" "-\t\t\t#size-cells = <1>;\n" "-\t\t\tranges = <0 3 0 0x200000>;\n" "-\n" - "-\t\t\tv2m_sysreg: sysreg@010000 {\n" + "-\t\t\tv2m_sysreg: sysreg at 010000 {\n" "-\t\t\t\tcompatible = \"arm,vexpress-sysreg\";\n" "-\t\t\t\treg = <0x010000 0x1000>;\n" "-\t\t\t};\n" "-\n" - "-\t\t\tv2m_serial0: uart@090000 {\n" + "-\t\t\tv2m_serial0: uart at 090000 {\n" "-\t\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "-\t\t\t\treg = <0x090000 0x1000>;\n" "-\t\t\t\tinterrupts = <5>;\n" @@ -1879,7 +1870,7 @@ "-\t\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\tv2m_serial1: uart@0a0000 {\n" + "-\t\t\tv2m_serial1: uart at 0a0000 {\n" "-\t\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "-\t\t\t\treg = <0x0a0000 0x1000>;\n" "-\t\t\t\tinterrupts = <6>;\n" @@ -1887,7 +1878,7 @@ "-\t\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\tv2m_serial2: uart@0b0000 {\n" + "-\t\t\tv2m_serial2: uart at 0b0000 {\n" "-\t\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "-\t\t\t\treg = <0x0b0000 0x1000>;\n" "-\t\t\t\tinterrupts = <7>;\n" @@ -1895,7 +1886,7 @@ "-\t\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\tv2m_serial3: uart@0c0000 {\n" + "-\t\t\tv2m_serial3: uart at 0c0000 {\n" "-\t\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "-\t\t\t\treg = <0x0c0000 0x1000>;\n" "-\t\t\t\tinterrupts = <8>;\n" @@ -1903,7 +1894,7 @@ "-\t\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\tvirtio_block@0130000 {\n" + "-\t\t\tvirtio_block at 0130000 {\n" "-\t\t\t\tcompatible = \"virtio,mmio\";\n" "-\t\t\t\treg = <0x130000 0x200>;\n" "-\t\t\t\tinterrupts = <42>;\n" @@ -1950,28 +1941,28 @@ "-\t\t#address-cells = <2>;\n" "-\t\t#size-cells = <0>;\n" "-\n" - "-\t\tcpu@0 {\n" + "-\t\tcpu at 0 {\n" "-\t\t\tdevice_type = \"cpu\";\n" "-\t\t\tcompatible = \"arm,armv8\";\n" "-\t\t\treg = <0x0 0x0>;\n" "-\t\t\tenable-method = \"spin-table\";\n" "-\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "-\t\t};\n" - "-\t\tcpu@1 {\n" + "-\t\tcpu at 1 {\n" "-\t\t\tdevice_type = \"cpu\";\n" "-\t\t\tcompatible = \"arm,armv8\";\n" "-\t\t\treg = <0x0 0x1>;\n" "-\t\t\tenable-method = \"spin-table\";\n" "-\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "-\t\t};\n" - "-\t\tcpu@2 {\n" + "-\t\tcpu at 2 {\n" "-\t\t\tdevice_type = \"cpu\";\n" "-\t\t\tcompatible = \"arm,armv8\";\n" "-\t\t\treg = <0x0 0x2>;\n" "-\t\t\tenable-method = \"spin-table\";\n" "-\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "-\t\t};\n" - "-\t\tcpu@3 {\n" + "-\t\tcpu at 3 {\n" "-\t\t\tdevice_type = \"cpu\";\n" "-\t\t\tcompatible = \"arm,armv8\";\n" "-\t\t\treg = <0x0 0x3>;\n" @@ -1980,13 +1971,13 @@ "-\t\t};\n" "-\t};\n" "-\n" - "-\tmemory@80000000 {\n" + "-\tmemory at 80000000 {\n" "-\t\tdevice_type = \"memory\";\n" "-\t\treg = <0x00000000 0x80000000 0 0x80000000>,\n" "-\t\t <0x00000008 0x80000000 0 0x80000000>;\n" "-\t};\n" "-\n" - "-\tgic: interrupt-controller@2c001000 {\n" + "-\tgic: interrupt-controller at 2c001000 {\n" "-\t\tcompatible = \"arm,cortex-a15-gic\", \"arm,cortex-a9-gic\";\n" "-\t\t#interrupt-cells = <3>;\n" "-\t\t#address-cells = <0>;\n" @@ -2099,19 +2090,19 @@ "-\t\t#interrupt-cells = <1>;\n" "-\t\tranges;\n" "-\n" - "-\t\tflash@0,00000000 {\n" + "-\t\tflash at 0,00000000 {\n" "-\t\t\tcompatible = \"arm,vexpress-flash\", \"cfi-flash\";\n" "-\t\t\treg = <0 0x00000000 0x04000000>,\n" "-\t\t\t <4 0x00000000 0x04000000>;\n" "-\t\t\tbank-width = <4>;\n" "-\t\t};\n" "-\n" - "-\t\tvram@2,00000000 {\n" + "-\t\tvram at 2,00000000 {\n" "-\t\t\tcompatible = \"arm,vexpress-vram\";\n" "-\t\t\treg = <2 0x00000000 0x00800000>;\n" "-\t\t};\n" "-\n" - "-\t\tethernet@2,02000000 {\n" + "-\t\tethernet at 2,02000000 {\n" "-\t\t\tcompatible = \"smsc,lan91c111\";\n" "-\t\t\treg = <2 0x02000000 0x10000>;\n" "-\t\t\tinterrupts = <15>;\n" @@ -2138,20 +2129,20 @@ "-\t\t\tclock-output-names = \"v2m:refclk32khz\";\n" "-\t\t};\n" "-\n" - "-\t\tiofpga@3,00000000 {\n" + "-\t\tiofpga at 3,00000000 {\n" "-\t\t\tcompatible = \"arm,amba-bus\", \"simple-bus\";\n" "-\t\t\t#address-cells = <1>;\n" "-\t\t\t#size-cells = <1>;\n" "-\t\t\tranges = <0 3 0 0x200000>;\n" "-\n" - "-\t\t\tv2m_sysreg: sysreg@010000 {\n" + "-\t\t\tv2m_sysreg: sysreg at 010000 {\n" "-\t\t\t\tcompatible = \"arm,vexpress-sysreg\";\n" "-\t\t\t\treg = <0x010000 0x1000>;\n" "-\t\t\t\tgpio-controller;\n" "-\t\t\t\t#gpio-cells = <2>;\n" "-\t\t\t};\n" "-\n" - "-\t\t\tv2m_sysctl: sysctl@020000 {\n" + "-\t\t\tv2m_sysctl: sysctl at 020000 {\n" "-\t\t\t\tcompatible = \"arm,sp810\", \"arm,primecell\";\n" "-\t\t\t\treg = <0x020000 0x1000>;\n" "-\t\t\t\tclocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;\n" @@ -2160,7 +2151,7 @@ "-\t\t\t\tclock-output-names = \"timerclken0\", \"timerclken1\", \"timerclken2\", \"timerclken3\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\taaci@040000 {\n" + "-\t\t\taaci at 040000 {\n" "-\t\t\t\tcompatible = \"arm,pl041\", \"arm,primecell\";\n" "-\t\t\t\treg = <0x040000 0x1000>;\n" "-\t\t\t\tinterrupts = <11>;\n" @@ -2168,7 +2159,7 @@ "-\t\t\t\tclock-names = \"apb_pclk\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\tmmci@050000 {\n" + "-\t\t\tmmci at 050000 {\n" "-\t\t\t\tcompatible = \"arm,pl180\", \"arm,primecell\";\n" "-\t\t\t\treg = <0x050000 0x1000>;\n" "-\t\t\t\tinterrupts = <9 10>;\n" @@ -2180,7 +2171,7 @@ "-\t\t\t\tclock-names = \"mclk\", \"apb_pclk\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\tkmi@060000 {\n" + "-\t\t\tkmi at 060000 {\n" "-\t\t\t\tcompatible = \"arm,pl050\", \"arm,primecell\";\n" "-\t\t\t\treg = <0x060000 0x1000>;\n" "-\t\t\t\tinterrupts = <12>;\n" @@ -2188,7 +2179,7 @@ "-\t\t\t\tclock-names = \"KMIREFCLK\", \"apb_pclk\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\tkmi@070000 {\n" + "-\t\t\tkmi at 070000 {\n" "-\t\t\t\tcompatible = \"arm,pl050\", \"arm,primecell\";\n" "-\t\t\t\treg = <0x070000 0x1000>;\n" "-\t\t\t\tinterrupts = <13>;\n" @@ -2196,7 +2187,7 @@ "-\t\t\t\tclock-names = \"KMIREFCLK\", \"apb_pclk\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\tv2m_serial0: uart@090000 {\n" + "-\t\t\tv2m_serial0: uart at 090000 {\n" "-\t\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "-\t\t\t\treg = <0x090000 0x1000>;\n" "-\t\t\t\tinterrupts = <5>;\n" @@ -2204,7 +2195,7 @@ "-\t\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\tv2m_serial1: uart@0a0000 {\n" + "-\t\t\tv2m_serial1: uart at 0a0000 {\n" "-\t\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "-\t\t\t\treg = <0x0a0000 0x1000>;\n" "-\t\t\t\tinterrupts = <6>;\n" @@ -2212,7 +2203,7 @@ "-\t\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\tv2m_serial2: uart@0b0000 {\n" + "-\t\t\tv2m_serial2: uart at 0b0000 {\n" "-\t\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "-\t\t\t\treg = <0x0b0000 0x1000>;\n" "-\t\t\t\tinterrupts = <7>;\n" @@ -2220,7 +2211,7 @@ "-\t\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\tv2m_serial3: uart@0c0000 {\n" + "-\t\t\tv2m_serial3: uart at 0c0000 {\n" "-\t\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n" "-\t\t\t\treg = <0x0c0000 0x1000>;\n" "-\t\t\t\tinterrupts = <8>;\n" @@ -2228,7 +2219,7 @@ "-\t\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\twdt@0f0000 {\n" + "-\t\t\twdt at 0f0000 {\n" "-\t\t\t\tcompatible = \"arm,sp805\", \"arm,primecell\";\n" "-\t\t\t\treg = <0x0f0000 0x1000>;\n" "-\t\t\t\tinterrupts = <0>;\n" @@ -2236,7 +2227,7 @@ "-\t\t\t\tclock-names = \"wdogclk\", \"apb_pclk\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\tv2m_timer01: timer@110000 {\n" + "-\t\t\tv2m_timer01: timer at 110000 {\n" "-\t\t\t\tcompatible = \"arm,sp804\", \"arm,primecell\";\n" "-\t\t\t\treg = <0x110000 0x1000>;\n" "-\t\t\t\tinterrupts = <2>;\n" @@ -2244,7 +2235,7 @@ "-\t\t\t\tclock-names = \"timclken1\", \"timclken2\", \"apb_pclk\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\tv2m_timer23: timer@120000 {\n" + "-\t\t\tv2m_timer23: timer at 120000 {\n" "-\t\t\t\tcompatible = \"arm,sp804\", \"arm,primecell\";\n" "-\t\t\t\treg = <0x120000 0x1000>;\n" "-\t\t\t\tinterrupts = <3>;\n" @@ -2252,7 +2243,7 @@ "-\t\t\t\tclock-names = \"timclken1\", \"timclken2\", \"apb_pclk\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\trtc@170000 {\n" + "-\t\t\trtc at 170000 {\n" "-\t\t\t\tcompatible = \"arm,pl031\", \"arm,primecell\";\n" "-\t\t\t\treg = <0x170000 0x1000>;\n" "-\t\t\t\tinterrupts = <4>;\n" @@ -2260,7 +2251,7 @@ "-\t\t\t\tclock-names = \"apb_pclk\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\tclcd@1f0000 {\n" + "-\t\t\tclcd at 1f0000 {\n" "-\t\t\t\tcompatible = \"arm,pl111\", \"arm,primecell\";\n" "-\t\t\t\treg = <0x1f0000 0x1000>;\n" "-\t\t\t\tinterrupts = <14>;\n" @@ -2268,14 +2259,14 @@ "-\t\t\t\tclock-names = \"clcdclk\", \"apb_pclk\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\tvirtio_block@0130000 {\n" + "-\t\t\tvirtio_block at 0130000 {\n" "-\t\t\t\tcompatible = \"virtio,mmio\";\n" "-\t\t\t\treg = <0x130000 0x200>;\n" "-\t\t\t\tinterrupts = <42>;\n" "-\t\t\t};\n" "-\t\t};\n" "-\n" - "-\t\tv2m_fixed_3v3: fixedregulator@0 {\n" + "-\t\tv2m_fixed_3v3: fixedregulator at 0 {\n" "-\t\t\tcompatible = \"regulator-fixed\";\n" "-\t\t\tregulator-name = \"3V3\";\n" "-\t\t\tregulator-min-microvolt = <3300000>;\n" @@ -2287,7 +2278,7 @@ "-\t\t\tcompatible = \"arm,vexpress,config-bus\";\n" "-\t\t\tarm,vexpress,config-bridge = <&v2m_sysreg>;\n" "-\n" - "-\t\t\tv2m_oscclk1: osc@1 {\n" + "-\t\t\tv2m_oscclk1: osc at 1 {\n" "-\t\t\t\t/* CLCD clock */\n" "-\t\t\t\tcompatible = \"arm,vexpress-osc\";\n" "-\t\t\t\tarm,vexpress-sysreg,func = <1 1>;\n" @@ -2296,27 +2287,27 @@ "-\t\t\t\tclock-output-names = \"v2m:oscclk1\";\n" "-\t\t\t};\n" "-\n" - "-\t\t\treset@0 {\n" + "-\t\t\treset at 0 {\n" "-\t\t\t\tcompatible = \"arm,vexpress-reset\";\n" "-\t\t\t\tarm,vexpress-sysreg,func = <5 0>;\n" "-\t\t\t};\n" "-\n" - "-\t\t\tmuxfpga@0 {\n" + "-\t\t\tmuxfpga at 0 {\n" "-\t\t\t\tcompatible = \"arm,vexpress-muxfpga\";\n" "-\t\t\t\tarm,vexpress-sysreg,func = <7 0>;\n" "-\t\t\t};\n" "-\n" - "-\t\t\tshutdown@0 {\n" + "-\t\t\tshutdown at 0 {\n" "-\t\t\t\tcompatible = \"arm,vexpress-shutdown\";\n" "-\t\t\t\tarm,vexpress-sysreg,func = <8 0>;\n" "-\t\t\t};\n" "-\n" - "-\t\t\treboot@0 {\n" + "-\t\t\treboot at 0 {\n" "-\t\t\t\tcompatible = \"arm,vexpress-reboot\";\n" "-\t\t\t\tarm,vexpress-sysreg,func = <9 0>;\n" "-\t\t\t};\n" "-\n" - "-\t\t\tdvimode@0 {\n" + "-\t\t\tdvimode at 0 {\n" "-\t\t\t\tcompatible = \"arm,vexpress-dvimode\";\n" "-\t\t\t\tarm,vexpress-sysreg,func = <11 0>;\n" "-\t\t\t};\n" @@ -2325,4 +2316,4 @@ "-- \n" 2.0.1 -09969769b91ce2a6852480a6ab4599be512b434fcdf77f554192651a28443de7 +af712ceffd4ba6bd78fb5c934875feb44a080f3bc954b3740724a61434fcf809
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