diff for duplicates of <1409957256-23729-18-git-send-email-sboyd@codeaurora.org> diff --git a/a/1.txt b/N1/1.txt index 474978f..89486d0 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -26,7 +26,7 @@ index 92bf793622c3..f01296bdb8f4 100644 + clock-latency = <100000>; }; - cpu@1 { + cpu at 1 { @@ -31,6 +34,9 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; @@ -36,7 +36,7 @@ index 92bf793622c3..f01296bdb8f4 100644 + clock-latency = <100000>; }; - cpu@2 { + cpu at 2 { @@ -41,6 +47,9 @@ next-level-cache = <&L2>; qcom,acc = <&acc2>; @@ -46,7 +46,7 @@ index 92bf793622c3..f01296bdb8f4 100644 + clock-latency = <100000>; }; - cpu@3 { + cpu at 3 { @@ -51,6 +60,9 @@ next-level-cache = <&L2>; qcom,acc = <&acc3>; @@ -273,37 +273,37 @@ index 92bf793622c3..f01296bdb8f4 100644 #address-cells = <1>; #size-cells = <1>; @@ -92,21 +312,31 @@ - acc0: clock-controller@2088000 { + acc0: clock-controller at 2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu0_aux"; }; - acc1: clock-controller@2098000 { + acc1: clock-controller at 2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu1_aux"; }; - acc2: clock-controller@20a8000 { + acc2: clock-controller at 20a8000 { compatible = "qcom,kpss-acc-v1"; reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu2_aux"; }; - acc3: clock-controller@20b8000 { + acc3: clock-controller at 20b8000 { compatible = "qcom,kpss-acc-v1"; reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu3_aux"; + }; + -+ l2cc: clock-controller@2011000 { ++ l2cc: clock-controller at 2011000 { + compatible = "qcom,kpss-gcc"; + reg = <0x2011000 0x1000>; + clock-output-names = "acpu_l2_aux"; }; - saw0: regulator@2089000 { + saw0: regulator at 2089000 { diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 5303e53e34dc..c034e3df2679 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -318,7 +318,7 @@ index 5303e53e34dc..c034e3df2679 100644 + }; - cpu@1 { + cpu at 1 { @@ -33,6 +37,10 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; @@ -371,25 +371,25 @@ index 5303e53e34dc..c034e3df2679 100644 #address-cells = <1>; #size-cells = <1>; @@ -100,11 +141,19 @@ - acc0: clock-controller@2088000 { + acc0: clock-controller at 2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu0_aux"; }; - acc1: clock-controller@2098000 { + acc1: clock-controller at 2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu1_aux"; + }; + -+ l2cc: clock-controller@2011000 { ++ l2cc: clock-controller at 2011000 { + compatible = "qcom,kpss-gcc"; + reg = <0x2011000 0x1000>; + clock-output-names = "acpu_l2_aux"; }; - saw0: regulator@2089000 { + saw0: regulator at 2089000 { diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 69dca2aca25a..567a40186136 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -398,8 +398,8 @@ index 69dca2aca25a..567a40186136 100644 #size-cells = <0>; interrupts = <1 9 0xf04>; -- cpu@0 { -+ cpu0: cpu@0 { +- cpu at 0 { ++ cpu0: cpu at 0 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; @@ -411,8 +411,8 @@ index 69dca2aca25a..567a40186136 100644 + clock-latency = <100000>; }; -- cpu@1 { -+ cpu1: cpu@1 { +- cpu at 1 { ++ cpu1: cpu at 1 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; @@ -424,8 +424,8 @@ index 69dca2aca25a..567a40186136 100644 + clock-latency = <100000>; }; -- cpu@2 { -+ cpu2: cpu@2 { +- cpu at 2 { ++ cpu2: cpu at 2 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; @@ -437,8 +437,8 @@ index 69dca2aca25a..567a40186136 100644 + clock-latency = <100000>; }; -- cpu@3 { -+ cpu3: cpu@3 { +- cpu at 3 { ++ cpu3: cpu at 3 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; @@ -723,37 +723,37 @@ index 69dca2aca25a..567a40186136 100644 }; }; -+ clock-controller@f9016000 { ++ clock-controller at f9016000 { + compatible = "qcom,hfpll"; + reg = <0xf9016000 0x30>; + clock-output-names = "hfpll_l2"; + }; + -+ clock-controller@f908a000 { ++ clock-controller at f908a000 { + compatible = "qcom,hfpll"; + reg = <0xf908a000 0x30>, <0xf900a000 0x30>; + clock-output-names = "hfpll0"; + }; + -+ clock-controller@f909a000 { ++ clock-controller at f909a000 { + compatible = "qcom,hfpll"; + reg = <0xf909a000 0x30>, <0xf900a000 0x30>; + clock-output-names = "hfpll1"; + }; + -+ clock-controller@f90aa000 { ++ clock-controller at f90aa000 { + compatible = "qcom,hfpll"; + reg = <0xf90aa000 0x30>, <0xf900a000 0x30>; + clock-output-names = "hfpll2"; + }; + -+ clock-controller@f90ba000 { ++ clock-controller at f90ba000 { + compatible = "qcom,hfpll"; + reg = <0xf90ba000 0x30>, <0xf900a000 0x30>; + clock-output-names = "hfpll3"; + }; + - saw_l2: regulator@f9012000 { + saw_l2: regulator at f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; -- diff --git a/a/content_digest b/N1/content_digest index 6c51909..695f9c7 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,13 +1,8 @@ "ref\01409957256-23729-1-git-send-email-sboyd@codeaurora.org\0" - "From\0Stephen Boyd <sboyd@codeaurora.org>\0" + "From\0sboyd@codeaurora.org (Stephen Boyd)\0" "Subject\0[PATCH v2 15/15] ARM: dts: qcom: Add necessary DT data for Krait cpufreq\0" "Date\0Fri, 5 Sep 2014 15:47:36 -0700\0" - "To\0Mike Turquette <mturquette@linaro.org>\0" - "Cc\0linux-kernel@vger.kernel.org" - linux-arm-msm@vger.kernel.org - linux-arm-kernel@lists.infradead.org - Viresh Kumar <viresh.kumar@linaro.org> - " linux-pm@vger.kernel.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Add the necessary DT nodes and data so we can probe the cpufreq\n" @@ -38,7 +33,7 @@ "+\t\t\tclock-latency = <100000>;\n" " \t\t};\n" " \n" - " \t\tcpu@1 {\n" + " \t\tcpu at 1 {\n" "@@ -31,6 +34,9 @@\n" " \t\t\tnext-level-cache = <&L2>;\n" " \t\t\tqcom,acc = <&acc1>;\n" @@ -48,7 +43,7 @@ "+\t\t\tclock-latency = <100000>;\n" " \t\t};\n" " \n" - " \t\tcpu@2 {\n" + " \t\tcpu at 2 {\n" "@@ -41,6 +47,9 @@\n" " \t\t\tnext-level-cache = <&L2>;\n" " \t\t\tqcom,acc = <&acc2>;\n" @@ -58,7 +53,7 @@ "+\t\t\tclock-latency = <100000>;\n" " \t\t};\n" " \n" - " \t\tcpu@3 {\n" + " \t\tcpu at 3 {\n" "@@ -51,6 +60,9 @@\n" " \t\t\tnext-level-cache = <&L2>;\n" " \t\t\tqcom,acc = <&acc3>;\n" @@ -285,37 +280,37 @@ " \t\t#address-cells = <1>;\n" " \t\t#size-cells = <1>;\n" "@@ -92,21 +312,31 @@\n" - " \t\tacc0: clock-controller@2088000 {\n" + " \t\tacc0: clock-controller at 2088000 {\n" " \t\t\tcompatible = \"qcom,kpss-acc-v1\";\n" " \t\t\treg = <0x02088000 0x1000>, <0x02008000 0x1000>;\n" "+\t\t\tclock-output-names = \"acpu0_aux\";\n" " \t\t};\n" " \n" - " \t\tacc1: clock-controller@2098000 {\n" + " \t\tacc1: clock-controller at 2098000 {\n" " \t\t\tcompatible = \"qcom,kpss-acc-v1\";\n" " \t\t\treg = <0x02098000 0x1000>, <0x02008000 0x1000>;\n" "+\t\t\tclock-output-names = \"acpu1_aux\";\n" " \t\t};\n" " \n" - " \t\tacc2: clock-controller@20a8000 {\n" + " \t\tacc2: clock-controller at 20a8000 {\n" " \t\t\tcompatible = \"qcom,kpss-acc-v1\";\n" " \t\t\treg = <0x020a8000 0x1000>, <0x02008000 0x1000>;\n" "+\t\t\tclock-output-names = \"acpu2_aux\";\n" " \t\t};\n" " \n" - " \t\tacc3: clock-controller@20b8000 {\n" + " \t\tacc3: clock-controller at 20b8000 {\n" " \t\t\tcompatible = \"qcom,kpss-acc-v1\";\n" " \t\t\treg = <0x020b8000 0x1000>, <0x02008000 0x1000>;\n" "+\t\t\tclock-output-names = \"acpu3_aux\";\n" "+\t\t};\n" "+\n" - "+\t\tl2cc: clock-controller@2011000 {\n" + "+\t\tl2cc: clock-controller at 2011000 {\n" "+\t\t\tcompatible = \"qcom,kpss-gcc\";\n" "+\t\t\treg = <0x2011000 0x1000>;\n" "+\t\t\tclock-output-names = \"acpu_l2_aux\";\n" " \t\t};\n" " \n" - " \t\tsaw0: regulator@2089000 {\n" + " \t\tsaw0: regulator at 2089000 {\n" "diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi\n" "index 5303e53e34dc..c034e3df2679 100644\n" "--- a/arch/arm/boot/dts/qcom-msm8960.dtsi\n" @@ -330,7 +325,7 @@ "+\n" " \t\t};\n" " \n" - " \t\tcpu@1 {\n" + " \t\tcpu at 1 {\n" "@@ -33,6 +37,10 @@\n" " \t\t\tnext-level-cache = <&L2>;\n" " \t\t\tqcom,acc = <&acc1>;\n" @@ -383,25 +378,25 @@ " \t\t#address-cells = <1>;\n" " \t\t#size-cells = <1>;\n" "@@ -100,11 +141,19 @@\n" - " \t\tacc0: clock-controller@2088000 {\n" + " \t\tacc0: clock-controller at 2088000 {\n" " \t\t\tcompatible = \"qcom,kpss-acc-v1\";\n" " \t\t\treg = <0x02088000 0x1000>, <0x02008000 0x1000>;\n" "+\t\t\tclock-output-names = \"acpu0_aux\";\n" " \t\t};\n" " \n" - " \t\tacc1: clock-controller@2098000 {\n" + " \t\tacc1: clock-controller at 2098000 {\n" " \t\t\tcompatible = \"qcom,kpss-acc-v1\";\n" " \t\t\treg = <0x02098000 0x1000>, <0x02008000 0x1000>;\n" "+\t\t\tclock-output-names = \"acpu1_aux\";\n" "+\t\t};\n" "+\n" - "+\t\tl2cc: clock-controller@2011000 {\n" + "+\t\tl2cc: clock-controller at 2011000 {\n" "+\t\t\tcompatible = \"qcom,kpss-gcc\";\n" "+\t\t\treg = <0x2011000 0x1000>;\n" "+\t\t\tclock-output-names = \"acpu_l2_aux\";\n" " \t\t};\n" " \n" - " \t\tsaw0: regulator@2089000 {\n" + " \t\tsaw0: regulator at 2089000 {\n" "diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi\n" "index 69dca2aca25a..567a40186136 100644\n" "--- a/arch/arm/boot/dts/qcom-msm8974.dtsi\n" @@ -410,8 +405,8 @@ " \t\t#size-cells = <0>;\n" " \t\tinterrupts = <1 9 0xf04>;\n" " \n" - "-\t\tcpu@0 {\n" - "+\t\tcpu0: cpu@0 {\n" + "-\t\tcpu at 0 {\n" + "+\t\tcpu0: cpu at 0 {\n" " \t\t\tcompatible = \"qcom,krait\";\n" " \t\t\tenable-method = \"qcom,kpss-acc-v2\";\n" " \t\t\tdevice_type = \"cpu\";\n" @@ -423,8 +418,8 @@ "+\t\t\tclock-latency = <100000>;\n" " \t\t};\n" " \n" - "-\t\tcpu@1 {\n" - "+\t\tcpu1: cpu@1 {\n" + "-\t\tcpu at 1 {\n" + "+\t\tcpu1: cpu at 1 {\n" " \t\t\tcompatible = \"qcom,krait\";\n" " \t\t\tenable-method = \"qcom,kpss-acc-v2\";\n" " \t\t\tdevice_type = \"cpu\";\n" @@ -436,8 +431,8 @@ "+\t\t\tclock-latency = <100000>;\n" " \t\t};\n" " \n" - "-\t\tcpu@2 {\n" - "+\t\tcpu2: cpu@2 {\n" + "-\t\tcpu at 2 {\n" + "+\t\tcpu2: cpu at 2 {\n" " \t\t\tcompatible = \"qcom,krait\";\n" " \t\t\tenable-method = \"qcom,kpss-acc-v2\";\n" " \t\t\tdevice_type = \"cpu\";\n" @@ -449,8 +444,8 @@ "+\t\t\tclock-latency = <100000>;\n" " \t\t};\n" " \n" - "-\t\tcpu@3 {\n" - "+\t\tcpu3: cpu@3 {\n" + "-\t\tcpu at 3 {\n" + "+\t\tcpu3: cpu at 3 {\n" " \t\t\tcompatible = \"qcom,krait\";\n" " \t\t\tenable-method = \"qcom,kpss-acc-v2\";\n" " \t\t\tdevice_type = \"cpu\";\n" @@ -735,41 +730,41 @@ " \t\t\t};\n" " \t\t};\n" " \n" - "+\t\tclock-controller@f9016000 {\n" + "+\t\tclock-controller at f9016000 {\n" "+\t\t\tcompatible = \"qcom,hfpll\";\n" "+\t\t\treg = <0xf9016000 0x30>;\n" "+\t\t\tclock-output-names = \"hfpll_l2\";\n" "+\t\t};\n" "+\n" - "+\t\tclock-controller@f908a000 {\n" + "+\t\tclock-controller at f908a000 {\n" "+\t\t\tcompatible = \"qcom,hfpll\";\n" "+\t\t\treg = <0xf908a000 0x30>, <0xf900a000 0x30>;\n" "+\t\t\tclock-output-names = \"hfpll0\";\n" "+\t\t};\n" "+\n" - "+\t\tclock-controller@f909a000 {\n" + "+\t\tclock-controller at f909a000 {\n" "+\t\t\tcompatible = \"qcom,hfpll\";\n" "+\t\t\treg = <0xf909a000 0x30>, <0xf900a000 0x30>;\n" "+\t\t\tclock-output-names = \"hfpll1\";\n" "+\t\t};\n" "+\n" - "+\t\tclock-controller@f90aa000 {\n" + "+\t\tclock-controller at f90aa000 {\n" "+\t\t\tcompatible = \"qcom,hfpll\";\n" "+\t\t\treg = <0xf90aa000 0x30>, <0xf900a000 0x30>;\n" "+\t\t\tclock-output-names = \"hfpll2\";\n" "+\t\t};\n" "+\n" - "+\t\tclock-controller@f90ba000 {\n" + "+\t\tclock-controller at f90ba000 {\n" "+\t\t\tcompatible = \"qcom,hfpll\";\n" "+\t\t\treg = <0xf90ba000 0x30>, <0xf900a000 0x30>;\n" "+\t\t\tclock-output-names = \"hfpll3\";\n" "+\t\t};\n" "+\n" - " \t\tsaw_l2: regulator@f9012000 {\n" + " \t\tsaw_l2: regulator at f9012000 {\n" " \t\t\tcompatible = \"qcom,saw2\";\n" " \t\t\treg = <0xf9012000 0x1000>;\n" "-- \n" "The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\n" hosted by The Linux Foundation -3b0ada78270cda39573b913cee770e11bcf94dd6c29e1f284ba80888d63f3812 +a3d6fe65ac419a2caa65adc968f7c523b5a6d4967fff3951ec9a1120d87ef220
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