From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from na01-bn1-obe.outbound.protection.outlook.com (mail-bn1bon0110.outbound.protection.outlook.com [157.56.111.110]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id CD5001A006C for ; Fri, 26 Sep 2014 06:08:19 +1000 (EST) Message-ID: <1411675680.13320.201.camel@snotra.buserror.net> Subject: Re: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add CLK_OF_DECLARE support From: Scott Wood To: Lu Jingchang-B35083 Date: Thu, 25 Sep 2014 15:08:00 -0500 In-Reply-To: References: <1411454806-8214-1-git-send-email-jingchang.lu@freescale.com> Content-Type: text/plain; charset="UTF-8" MIME-Version: 1.0 Cc: "linuxppc-dev@lists.ozlabs.org" , "mturquette@linaro.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Well, like I said, I'd rather see the CLK_OF_DECLARE stuff be made to work on PPC rather than have the driver carry around two binding methods. -Scott On Thu, 2014-09-25 at 04:47 -0500, Lu Jingchang-B35083 wrote: > Hi, Scott and Mike, > > Could you please help review this patch and give an ACK if ok. Thanks. > > Best Regards, > Jingchang > > >-----Original Message----- > >From: Jingchang Lu [mailto:jingchang.lu@freescale.com] > >Sent: Tuesday, September 23, 2014 2:47 PM > >To: mturquette@linaro.org > >Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; linux- > >kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Lu > >Jingchang-B35083 > >Subject: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add > >CLK_OF_DECLARE support > > > >The IP is shared by PPC and ARM, this renames it to qoriq for better > >represention, and this also adds the CLK_OF_DECLARE support for being > >initialized by of_clk_init() on ARM. > > > >Signed-off-by: Jingchang Lu > >--- > >changes in v4: > > remove "corenet" literals omitted in v3 remove. > > > >changes in v3: > > generate the patch with -M -C option > > > >changes in v2: > > rename the driver name to ppc-qoriq.c for shared on PPC and ARM. > > > > drivers/clk/Kconfig | 9 +++++---- > > drivers/clk/Makefile | 2 +- > > drivers/clk/{clk-ppc-corenet.c => clk-qoriq.c} | 27 +++++++++++++++------ > >----- > > 3 files changed, 22 insertions(+), 16 deletions(-) rename > >drivers/clk/{clk-ppc-corenet.c => clk-qoriq.c} (89%) > > > >diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index > >85131ae..f5f76cb 100644 > >--- a/drivers/clk/Kconfig > >+++ b/drivers/clk/Kconfig > >@@ -92,12 +92,13 @@ config COMMON_CLK_AXI_CLKGEN > > Support for the Analog Devices axi-clkgen pcore clock generator > >for Xilinx > > FPGAs. It is commonly used in Analog Devices' reference designs. > > > >-config CLK_PPC_CORENET > >- bool "Clock driver for PowerPC corenet platforms" > >- depends on PPC_E500MC && OF > >+config CLK_QORIQ > >+ bool "Clock driver for PowerPC corenet and compatible ARM-based > >platforms" > >+ depends on (PPC_E500MC || ARM) && OF > > ---help--- > > This adds the clock driver support for Freescale PowerPC corenet > >- platforms using common clock framework. > >+ platforms and compatible Freescale ARM based platforms using > >common > >+ clock framework. > > > > config COMMON_CLK_XGENE > > bool "Clock driver for APM XGene SoC" > >diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index > >27c542b..20f42e9 100644 > >--- a/drivers/clk/Makefile > >+++ b/drivers/clk/Makefile > >@@ -29,7 +29,7 @@ obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o > > obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o > > obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o > > obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o > >-obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o > >+obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o > > obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o > > obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o > > obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o > >diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-qoriq.c > >similarity index 89% rename from drivers/clk/clk-ppc-corenet.c rename to > >drivers/clk/clk-qoriq.c index 8e58edf..cba8abe 100644 > >--- a/drivers/clk/clk-ppc-corenet.c > >+++ b/drivers/clk/clk-qoriq.c > >@@ -155,7 +155,7 @@ static void __init core_pll_init(struct device_node > >*np) > > > > base = of_iomap(np, 0); > > if (!base) { > >- pr_err("clk-ppc: iomap error\n"); > >+ pr_err("clk-qoriq: iomap error\n"); > > return; > > } > > > >@@ -252,7 +252,7 @@ static void __init sysclk_init(struct device_node > >*node) > > u32 rate; > > > > if (!np) { > >- pr_err("ppc-clk: could not get parent node\n"); > >+ pr_err("qoriq-clk: could not get parent node\n"); > > return; > > } > > > >@@ -278,30 +278,35 @@ static const struct of_device_id clk_match[] > >__initconst = { > > {} > > }; > > > >-static int __init ppc_corenet_clk_probe(struct platform_device *pdev) > >+static int __init qoriq_clk_probe(struct platform_device *pdev) > > { > > of_clk_init(clk_match); > > > > return 0; > > } > > > >-static const struct of_device_id ppc_clk_ids[] __initconst = { > >+static const struct of_device_id qoriq_clk_ids[] __initconst = { > > { .compatible = "fsl,qoriq-clockgen-1.0", }, > > { .compatible = "fsl,qoriq-clockgen-2.0", }, > > {} > > }; > > > >-static struct platform_driver ppc_corenet_clk_driver __initdata = { > >+static struct platform_driver qoriq_clk_driver __initdata = { > > .driver = { > >- .name = "ppc_corenet_clock", > >+ .name = "qoriq_clock", > > .owner = THIS_MODULE, > >- .of_match_table = ppc_clk_ids, > >+ .of_match_table = qoriq_clk_ids, > > }, > >- .probe = ppc_corenet_clk_probe, > >+ .probe = qoriq_clk_probe, > > }; > > > >-static int __init ppc_corenet_clk_init(void) > >+static int __init qoriq_clk_init(void) > > { > >- return platform_driver_register(&ppc_corenet_clk_driver); > >+ return platform_driver_register(&qoriq_clk_driver); > > } > >-subsys_initcall(ppc_corenet_clk_init); > >+subsys_initcall(qoriq_clk_init); > >+ > >+CLK_OF_DECLARE(qoriq_core_pll_v1, "fsl,qoriq-core-pll-1.0", > >+core_pll_init); CLK_OF_DECLARE(qoriq_core_pll_v2, > >+"fsl,qoriq-core-pll-2.0", core_pll_init); > >+CLK_OF_DECLARE(qoriq_core_mux_v1, "fsl,qoriq-core-mux-1.0", > >+core_mux_init); CLK_OF_DECLARE(qoriq_core_mux_v2, > >+"fsl,qoriq-core-mux-2.0", core_mux_init); > >-- > >1.8.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 From: scottwood@freescale.com (Scott Wood) Date: Thu, 25 Sep 2014 15:08:00 -0500 Subject: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add CLK_OF_DECLARE support In-Reply-To: References: <1411454806-8214-1-git-send-email-jingchang.lu@freescale.com> Message-ID: <1411675680.13320.201.camel@snotra.buserror.net> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Well, like I said, I'd rather see the CLK_OF_DECLARE stuff be made to work on PPC rather than have the driver carry around two binding methods. -Scott On Thu, 2014-09-25 at 04:47 -0500, Lu Jingchang-B35083 wrote: > Hi, Scott and Mike, > > Could you please help review this patch and give an ACK if ok. Thanks. > > Best Regards, > Jingchang > > >-----Original Message----- > >From: Jingchang Lu [mailto:jingchang.lu at freescale.com] > >Sent: Tuesday, September 23, 2014 2:47 PM > >To: mturquette at linaro.org > >Cc: Wood Scott-B07421; linuxppc-dev at lists.ozlabs.org; linux- > >kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Lu > >Jingchang-B35083 > >Subject: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add > >CLK_OF_DECLARE support > > > >The IP is shared by PPC and ARM, this renames it to qoriq for better > >represention, and this also adds the CLK_OF_DECLARE support for being > >initialized by of_clk_init() on ARM. > > > >Signed-off-by: Jingchang Lu > >--- > >changes in v4: > > remove "corenet" literals omitted in v3 remove. > > > >changes in v3: > > generate the patch with -M -C option > > > >changes in v2: > > rename the driver name to ppc-qoriq.c for shared on PPC and ARM. > > > > drivers/clk/Kconfig | 9 +++++---- > > drivers/clk/Makefile | 2 +- > > drivers/clk/{clk-ppc-corenet.c => clk-qoriq.c} | 27 +++++++++++++++------ > >----- > > 3 files changed, 22 insertions(+), 16 deletions(-) rename > >drivers/clk/{clk-ppc-corenet.c => clk-qoriq.c} (89%) > > > >diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index > >85131ae..f5f76cb 100644 > >--- a/drivers/clk/Kconfig > >+++ b/drivers/clk/Kconfig > >@@ -92,12 +92,13 @@ config COMMON_CLK_AXI_CLKGEN > > Support for the Analog Devices axi-clkgen pcore clock generator > >for Xilinx > > FPGAs. It is commonly used in Analog Devices' reference designs. > > > >-config CLK_PPC_CORENET > >- bool "Clock driver for PowerPC corenet platforms" > >- depends on PPC_E500MC && OF > >+config CLK_QORIQ > >+ bool "Clock driver for PowerPC corenet and compatible ARM-based > >platforms" > >+ depends on (PPC_E500MC || ARM) && OF > > ---help--- > > This adds the clock driver support for Freescale PowerPC corenet > >- platforms using common clock framework. > >+ platforms and compatible Freescale ARM based platforms using > >common > >+ clock framework. > > > > config COMMON_CLK_XGENE > > bool "Clock driver for APM XGene SoC" > >diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index > >27c542b..20f42e9 100644 > >--- a/drivers/clk/Makefile > >+++ b/drivers/clk/Makefile > >@@ -29,7 +29,7 @@ obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o > > obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o > > obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o > > obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o > >-obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o > >+obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o > > obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o > > obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o > > obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o > >diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-qoriq.c > >similarity index 89% rename from drivers/clk/clk-ppc-corenet.c rename to > >drivers/clk/clk-qoriq.c index 8e58edf..cba8abe 100644 > >--- a/drivers/clk/clk-ppc-corenet.c > >+++ b/drivers/clk/clk-qoriq.c > >@@ -155,7 +155,7 @@ static void __init core_pll_init(struct device_node > >*np) > > > > base = of_iomap(np, 0); > > if (!base) { > >- pr_err("clk-ppc: iomap error\n"); > >+ pr_err("clk-qoriq: iomap error\n"); > > return; > > } > > > >@@ -252,7 +252,7 @@ static void __init sysclk_init(struct device_node > >*node) > > u32 rate; > > > > if (!np) { > >- pr_err("ppc-clk: could not get parent node\n"); > >+ pr_err("qoriq-clk: could not get parent node\n"); > > return; > > } > > > >@@ -278,30 +278,35 @@ static const struct of_device_id clk_match[] > >__initconst = { > > {} > > }; > > > >-static int __init ppc_corenet_clk_probe(struct platform_device *pdev) > >+static int __init qoriq_clk_probe(struct platform_device *pdev) > > { > > of_clk_init(clk_match); > > > > return 0; > > } > > > >-static const struct of_device_id ppc_clk_ids[] __initconst = { > >+static const struct of_device_id qoriq_clk_ids[] __initconst = { > > { .compatible = "fsl,qoriq-clockgen-1.0", }, > > { .compatible = "fsl,qoriq-clockgen-2.0", }, > > {} > > }; > > > >-static struct platform_driver ppc_corenet_clk_driver __initdata = { > >+static struct platform_driver qoriq_clk_driver __initdata = { > > .driver = { > >- .name = "ppc_corenet_clock", > >+ .name = "qoriq_clock", > > .owner = THIS_MODULE, > >- .of_match_table = ppc_clk_ids, > >+ .of_match_table = qoriq_clk_ids, > > }, > >- .probe = ppc_corenet_clk_probe, > >+ .probe = qoriq_clk_probe, > > }; > > > >-static int __init ppc_corenet_clk_init(void) > >+static int __init qoriq_clk_init(void) > > { > >- return platform_driver_register(&ppc_corenet_clk_driver); > >+ return platform_driver_register(&qoriq_clk_driver); > > } > >-subsys_initcall(ppc_corenet_clk_init); > >+subsys_initcall(qoriq_clk_init); > >+ > >+CLK_OF_DECLARE(qoriq_core_pll_v1, "fsl,qoriq-core-pll-1.0", > >+core_pll_init); CLK_OF_DECLARE(qoriq_core_pll_v2, > >+"fsl,qoriq-core-pll-2.0", core_pll_init); > >+CLK_OF_DECLARE(qoriq_core_mux_v1, "fsl,qoriq-core-mux-1.0", > >+core_mux_init); CLK_OF_DECLARE(qoriq_core_mux_v2, > >+"fsl,qoriq-core-mux-2.0", core_mux_init); > >-- > >1.8.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752243AbaIYUIN (ORCPT ); Thu, 25 Sep 2014 16:08:13 -0400 Received: from mail-bn1bon0140.outbound.protection.outlook.com ([157.56.111.140]:15168 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751939AbaIYUIM (ORCPT ); Thu, 25 Sep 2014 16:08:12 -0400 Message-ID: <1411675680.13320.201.camel@snotra.buserror.net> Subject: Re: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add CLK_OF_DECLARE support From: Scott Wood To: Lu Jingchang-B35083 CC: "mturquette@linaro.org" , "linuxppc-dev@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Date: Thu, 25 Sep 2014 15:08:00 -0500 In-Reply-To: References: <1411454806-8214-1-git-send-email-jingchang.lu@freescale.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Originating-IP: [2601:2:5800:3f7:416f:c6f:49e6:9e61] X-ClientProxiedBy: BLUPR08CA0071.namprd08.prod.outlook.com (10.141.200.51) To BY2PR0301MB0728.namprd03.prod.outlook.com (25.160.63.18) X-Microsoft-Antispam: UriScan:; X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;SRVR:BY2PR0301MB0728; X-Forefront-PRVS: 0345CFD558 X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10019020)(6009001)(24454002)(13464003)(51704005)(189002)(377424004)(377454003)(199003)(92566001)(106356001)(95666004)(21056001)(42186005)(50466002)(104166001)(76482002)(50226001)(120916001)(62966002)(10300001)(97736003)(81342003)(77156001)(74502003)(77096002)(86362001)(90102001)(33646002)(77982003)(105586002)(47776003)(80022003)(20776003)(85306004)(101416001)(85852003)(23676002)(4396001)(79102003)(88136002)(31966008)(107046002)(19580405001)(76176999)(83072002)(110136001)(102836001)(64706001)(83322001)(103116003)(93916002)(74662003)(46102003)(81542003)(89996001)(19580395003)(87976001)(99396003)(50986999)(87286001)(92726001)(3826002);DIR:OUT;SFP:1102;SCL:1;SRVR:BY2PR0301MB0728;H:[IPv6:2601:2:5800:3f7:416f:c6f:49e6:9e61];FPR:;MLV:sfv;PTR:InfoNoRecords;MX:1;A:1;LANG:en; X-OriginatorOrg: freescale.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Well, like I said, I'd rather see the CLK_OF_DECLARE stuff be made to work on PPC rather than have the driver carry around two binding methods. -Scott On Thu, 2014-09-25 at 04:47 -0500, Lu Jingchang-B35083 wrote: > Hi, Scott and Mike, > > Could you please help review this patch and give an ACK if ok. Thanks. > > Best Regards, > Jingchang > > >-----Original Message----- > >From: Jingchang Lu [mailto:jingchang.lu@freescale.com] > >Sent: Tuesday, September 23, 2014 2:47 PM > >To: mturquette@linaro.org > >Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; linux- > >kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Lu > >Jingchang-B35083 > >Subject: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add > >CLK_OF_DECLARE support > > > >The IP is shared by PPC and ARM, this renames it to qoriq for better > >represention, and this also adds the CLK_OF_DECLARE support for being > >initialized by of_clk_init() on ARM. > > > >Signed-off-by: Jingchang Lu > >--- > >changes in v4: > > remove "corenet" literals omitted in v3 remove. > > > >changes in v3: > > generate the patch with -M -C option > > > >changes in v2: > > rename the driver name to ppc-qoriq.c for shared on PPC and ARM. > > > > drivers/clk/Kconfig | 9 +++++---- > > drivers/clk/Makefile | 2 +- > > drivers/clk/{clk-ppc-corenet.c => clk-qoriq.c} | 27 +++++++++++++++------ > >----- > > 3 files changed, 22 insertions(+), 16 deletions(-) rename > >drivers/clk/{clk-ppc-corenet.c => clk-qoriq.c} (89%) > > > >diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index > >85131ae..f5f76cb 100644 > >--- a/drivers/clk/Kconfig > >+++ b/drivers/clk/Kconfig > >@@ -92,12 +92,13 @@ config COMMON_CLK_AXI_CLKGEN > > Support for the Analog Devices axi-clkgen pcore clock generator > >for Xilinx > > FPGAs. It is commonly used in Analog Devices' reference designs. > > > >-config CLK_PPC_CORENET > >- bool "Clock driver for PowerPC corenet platforms" > >- depends on PPC_E500MC && OF > >+config CLK_QORIQ > >+ bool "Clock driver for PowerPC corenet and compatible ARM-based > >platforms" > >+ depends on (PPC_E500MC || ARM) && OF > > ---help--- > > This adds the clock driver support for Freescale PowerPC corenet > >- platforms using common clock framework. > >+ platforms and compatible Freescale ARM based platforms using > >common > >+ clock framework. > > > > config COMMON_CLK_XGENE > > bool "Clock driver for APM XGene SoC" > >diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index > >27c542b..20f42e9 100644 > >--- a/drivers/clk/Makefile > >+++ b/drivers/clk/Makefile > >@@ -29,7 +29,7 @@ obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o > > obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o > > obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o > > obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o > >-obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o > >+obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o > > obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o > > obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o > > obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o > >diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-qoriq.c > >similarity index 89% rename from drivers/clk/clk-ppc-corenet.c rename to > >drivers/clk/clk-qoriq.c index 8e58edf..cba8abe 100644 > >--- a/drivers/clk/clk-ppc-corenet.c > >+++ b/drivers/clk/clk-qoriq.c > >@@ -155,7 +155,7 @@ static void __init core_pll_init(struct device_node > >*np) > > > > base = of_iomap(np, 0); > > if (!base) { > >- pr_err("clk-ppc: iomap error\n"); > >+ pr_err("clk-qoriq: iomap error\n"); > > return; > > } > > > >@@ -252,7 +252,7 @@ static void __init sysclk_init(struct device_node > >*node) > > u32 rate; > > > > if (!np) { > >- pr_err("ppc-clk: could not get parent node\n"); > >+ pr_err("qoriq-clk: could not get parent node\n"); > > return; > > } > > > >@@ -278,30 +278,35 @@ static const struct of_device_id clk_match[] > >__initconst = { > > {} > > }; > > > >-static int __init ppc_corenet_clk_probe(struct platform_device *pdev) > >+static int __init qoriq_clk_probe(struct platform_device *pdev) > > { > > of_clk_init(clk_match); > > > > return 0; > > } > > > >-static const struct of_device_id ppc_clk_ids[] __initconst = { > >+static const struct of_device_id qoriq_clk_ids[] __initconst = { > > { .compatible = "fsl,qoriq-clockgen-1.0", }, > > { .compatible = "fsl,qoriq-clockgen-2.0", }, > > {} > > }; > > > >-static struct platform_driver ppc_corenet_clk_driver __initdata = { > >+static struct platform_driver qoriq_clk_driver __initdata = { > > .driver = { > >- .name = "ppc_corenet_clock", > >+ .name = "qoriq_clock", > > .owner = THIS_MODULE, > >- .of_match_table = ppc_clk_ids, > >+ .of_match_table = qoriq_clk_ids, > > }, > >- .probe = ppc_corenet_clk_probe, > >+ .probe = qoriq_clk_probe, > > }; > > > >-static int __init ppc_corenet_clk_init(void) > >+static int __init qoriq_clk_init(void) > > { > >- return platform_driver_register(&ppc_corenet_clk_driver); > >+ return platform_driver_register(&qoriq_clk_driver); > > } > >-subsys_initcall(ppc_corenet_clk_init); > >+subsys_initcall(qoriq_clk_init); > >+ > >+CLK_OF_DECLARE(qoriq_core_pll_v1, "fsl,qoriq-core-pll-1.0", > >+core_pll_init); CLK_OF_DECLARE(qoriq_core_pll_v2, > >+"fsl,qoriq-core-pll-2.0", core_pll_init); > >+CLK_OF_DECLARE(qoriq_core_mux_v1, "fsl,qoriq-core-mux-1.0", > >+core_mux_init); CLK_OF_DECLARE(qoriq_core_mux_v2, > >+"fsl,qoriq-core-mux-2.0", core_mux_init); > >-- > >1.8.0 >