From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: Re: [PATCH] arm32: fix build after 063188f4b3 Date: Fri, 10 Oct 2014 16:26:33 +0100 Message-ID: <1412954793.27111.53.camel@eu.citrix.com> References: <54380211020000780003DC42@mail.emea.novell.com> <1412950621.27111.29.camel@eu.citrix.com> <54380F2C020000780003DD9A@mail.emea.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Xcc66-00079z-KM for xen-devel@lists.xenproject.org; Fri, 10 Oct 2014 15:27:14 +0000 In-Reply-To: <54380F2C020000780003DD9A@mail.emea.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich Cc: Suriyan Ramasami , TimDeegan , Stefano Stabellini , xen-devel List-Id: xen-devel@lists.xenproject.org On Fri, 2014-10-10 at 15:54 +0100, Jan Beulich wrote: > >>> On 10.10.14 at 16:17, wrote: > > On Fri, 2014-10-10 at 14:58 +0100, Jan Beulich wrote: > >> static noinline void exynos_smc(register_t function_id, register_t arg0, > >> register_t arg1, register_t arg2) > >> { > >> + register register_t fn_id asm("r0") = function_id; > >> + register register_t a0 asm("r1") = arg0; > >> + register register_t a1 asm("r2") = arg1; > >> + register register_t a2 asm("r3") = arg2; > > > > ISTR being told that the arm gcc backend pays this sort of asm("r1") > > thing no heed (it's x86 specific?). This is how we ended up with the > > asmeq -- it was what the arm compiler guys (via the arm kernels guys) > > recommended. > > It is formally documented to play by this, You made me look again and here it is https://gcc.gnu.org/onlinedocs/gcc/Local-Reg-Vars.html > so I don't think this is > x86 specific, and I would strongly suspect any (apparent) violation > of this to be either a misunderstanding of the guarantees that are > being made or a bug in the specific compiler version. I may well be misremembering the older discussions... Either way, you retained the asmeq bits so even if there are broken gcc's out there we won't produce broken binaries and your patch is a clear improvement IMHO. > > Stefano may remember better (since this was in the context of the Linux > > hypervisor stub). > > > > I suppose you have a compiler which tickles this? > > Yes, the gcc 4.9.1 I use for testing the ARM builds. I'm still on 4.8, I'll grab a 4.9 and use it occasionally... Ian.