From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: Re: [PATCH v8 3/8] xen/arm: return int *_dcache_va_range Date: Mon, 20 Oct 2014 15:57:26 +0100 Message-ID: <1413817046.13796.21.camel@citrix.com> References: <1413798499-28314-3-git-send-email-stefano.stabellini@eu.citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1413798499-28314-3-git-send-email-stefano.stabellini@eu.citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Stefano Stabellini Cc: julien.grall@citrix.com, xen-devel@lists.xensource.com, JBeulich@suse.com List-Id: xen-devel@lists.xenproject.org On Mon, 2014-10-20 at 10:48 +0100, Stefano Stabellini wrote: > These functions cannot really fail on ARM, but their x86 equivalents can > (-EOPNOTSUPP). Change the prototype to return int. The subject seems to be missing a word (from?), or is somehow garbled. > Signed-off-by: Stefano Stabellini > Reviewed-by: Julien Grall > > --- > > Changes in v6: > - do not return int from flush_page_to_ram. > --- > xen/arch/arm/mm.c | 2 +- > xen/include/asm-arm/page.h | 6 ++++-- > 2 files changed, 5 insertions(+), 3 deletions(-) > > diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c > index e43499a..8e989bf 100644 > --- a/xen/arch/arm/mm.c > +++ b/xen/arch/arm/mm.c > @@ -388,7 +388,7 @@ void flush_page_to_ram(unsigned long mfn) > { > void *v = map_domain_page(mfn); > > - clean_and_invalidate_dcache_va_range(v, PAGE_SIZE); > + ASSERT(clean_and_invalidate_dcache_va_range(v, PAGE_SIZE) == 0); Just this one assert? What about all the other callers of *_dcache_va_range? > unmap_domain_page(v); > } > > diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h > index 1327b00..26c5856 100644 > --- a/xen/include/asm-arm/page.h > +++ b/xen/include/asm-arm/page.h > @@ -268,16 +268,17 @@ extern size_t cacheline_bytes; > /* Functions for flushing medium-sized areas. > * if 'range' is large enough we might want to use model-specific > * full-cache flushes. */ > -static inline void clean_dcache_va_range(const void *p, unsigned long size) > +static inline int clean_dcache_va_range(const void *p, unsigned long size) > { > const void *end; > dsb(sy); /* So the CPU issues all writes to the range */ > for ( end = p + size; p < end; p += cacheline_bytes ) > asm volatile (__clean_dcache_one(0) : : "r" (p)); > dsb(sy); /* So we know the flushes happen before continuing */ > + return 0; > } > > -static inline void clean_and_invalidate_dcache_va_range > +static inline int clean_and_invalidate_dcache_va_range > (const void *p, unsigned long size) > { > const void *end; > @@ -285,6 +286,7 @@ static inline void clean_and_invalidate_dcache_va_range > for ( end = p + size; p < end; p += cacheline_bytes ) > asm volatile (__clean_and_invalidate_dcache_one(0) : : "r" (p)); > dsb(sy); /* So we know the flushes happen before continuing */ > + return 0; > } > > /* Macros for flushing a single small item. The predicate is always