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From: Imre Deak <imre.deak@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org, paulo.r.zanoni@intel.com
Subject: Re: [PATCH v2 6/8] drm/i915: sanitize rps irq enabling
Date: Mon, 10 Nov 2014 16:13:02 +0200	[thread overview]
Message-ID: <1415628782.12176.38.camel@intelbox> (raw)
In-Reply-To: <20141110134532.GE22109@nuc-i3427.alporthouse.com>

On Mon, 2014-11-10 at 13:45 +0000, Chris Wilson wrote:
> On Mon, Nov 10, 2014 at 03:41:05PM +0200, Imre Deak wrote:
> > Atm we first enable the RPS interrupts then we clear any pending ones.
> > By this we could lose an interrupt arriving after we unmasked it. This
> > may not be a problem as the caller should handle such a race, but logic
> > still calls for the opposite order. Also we can delay enabling the
> > interrupts until after all the RPS initialization is ready with the
> > following order:
> > 
> 
> 0. disable left-over RPS

Isn't enough relying on
intel_uncore_sanitize()->intel_disable_gt_powersave()?

> > 1. clear any pending RPS interrupts
> > 2. initialize RPS
> > 3. enable RPS interrupts
> -Chris
> 


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  reply	other threads:[~2014-11-10 14:13 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-05 18:48 [PATCH 6/8] drm/i915: sanitize rps irq enabling Imre Deak
2014-11-10 13:41 ` [PATCH v2 " Imre Deak
2014-11-10 13:45   ` Chris Wilson
2014-11-10 14:13     ` Imre Deak [this message]
2014-11-10 14:15       ` Chris Wilson
2014-11-10 14:21         ` Imre Deak
2014-11-17 18:49   ` Paulo Zanoni
2014-11-17 19:05     ` Imre Deak

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