From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by yocto-www.yoctoproject.org (Postfix, from userid 118) id EEB3EE0092D; Wed, 3 Dec 2014 09:08:07 -0800 (PST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on yocto-www.yoctoproject.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.1 X-Spam-HAM-Report: * -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low * trust * [209.85.220.51 listed in list.dnswl.org] * 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider * (bisson.gary[at]gmail.com) * -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% * [score: 0.0000] * -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's * domain * 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily * valid * -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Received: from mail-pa0-f51.google.com (mail-pa0-f51.google.com [209.85.220.51]) by yocto-www.yoctoproject.org (Postfix) with ESMTP id 392D6E008F6 for ; Wed, 3 Dec 2014 09:07:57 -0800 (PST) Received: by mail-pa0-f51.google.com with SMTP id ey11so16237720pad.10 for ; Wed, 03 Dec 2014 09:07:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WwI7+C+PNGABxMIaUOEb9VATyLYEErs2XMnysmCan1g=; b=oye1ub/awvZoL9S/AwhGUiJEd0TZvBVKIFgTdIs2Xx5eSCpP+uhdXG6gsFgxEr+S1B TWlwWAldvDGbojFMiFaTG7N4RuzC6JN67x2hCLOUjSpRpOEqyyMXtDv1Xwv2/i26ZmY4 x/ds9OdRcqDUra1lY60oqIgyoXcUwzIgy4h6YFCPrZ58U0Ou9gRYXwoLs4Clgshaljuv khK/+jfWcm9+tMTLUJhaJ45j85WIhMDlMdZVSK4SraLXr9pyDWoThPSqcwUBLoWX4Qv+ sDhugKl1VSxfxHPl83d/djoGgySyuDXo72poI5nGM9oxhKnv3hVrmk3/0Wv7SuIWBttp gX+A== X-Received: by 10.70.129.48 with SMTP id nt16mr10095616pdb.113.1417626477336; Wed, 03 Dec 2014 09:07:57 -0800 (PST) Received: from n411z.WORKGROUP. (c-71-227-188-44.hsd1.wa.comcast.net. [71.227.188.44]) by mx.google.com with ESMTPSA id f12sm23616339pdm.90.2014.12.03.09.07.55 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 03 Dec 2014 09:07:56 -0800 (PST) From: Gary Bisson To: meta-freescale@yoctoproject.org Date: Wed, 3 Dec 2014 09:07:27 -0800 Message-Id: <1417626447-17194-3-git-send-email-bisson.gary@gmail.com> X-Mailer: git-send-email 2.1.3 In-Reply-To: <1417626447-17194-1-git-send-email-bisson.gary@gmail.com> References: <1417626447-17194-1-git-send-email-bisson.gary@gmail.com> Cc: fabio.estevam@freescale.com, Gary Bisson , otavio@ossystems.com.br Subject: [PATCH 2/2][dizzy-next] linux-imx: add clock patch for T1.0 version of i.MX6Q X-BeenThere: meta-freescale@yoctoproject.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Usage and development list for the meta-fsl-* layers List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 03 Dec 2014 17:08:08 -0000 A divider was still set to 4 instead of forcing it to 1 as those video dividers weren't working on early revisions of the SoC. Signed-off-by: Gary Bisson --- ...6q-fix-video-divider-for-revision-1.0-of-.patch | 33 ++++++++++++++++++++++ recipes-kernel/linux/linux-imx_3.10.17.bb | 2 ++ 2 files changed, 35 insertions(+) create mode 100644 recipes-kernel/linux/linux-imx-3.10.17/0001-ARM-clk-imx6q-fix-video-divider-for-revision-1.0-of-.patch diff --git a/recipes-kernel/linux/linux-imx-3.10.17/0001-ARM-clk-imx6q-fix-video-divider-for-revision-1.0-of-.patch b/recipes-kernel/linux/linux-imx-3.10.17/0001-ARM-clk-imx6q-fix-video-divider-for-revision-1.0-of-.patch new file mode 100644 index 0000000..bcddb16 --- /dev/null +++ b/recipes-kernel/linux/linux-imx-3.10.17/0001-ARM-clk-imx6q-fix-video-divider-for-revision-1.0-of-.patch @@ -0,0 +1,33 @@ +From ffcd8b98f6ba3a2b7a4aecc1e5e454de5fa5c4c3 Mon Sep 17 00:00:00 2001 +From: Gary Bisson +Date: Tue, 2 Dec 2014 22:11:14 -0800 +Subject: [PATCH] ARM: clk-imx6q: fix video divider for revision 1.0 of i.MX6q + +As post dividers do not work on i.MX6Q revision 1.0 they must be fixed +to 1. As the table index was wrong, a divider a of 4 could still be +requested which implied the clock not to be set properly. This is the +root cause of the HDMI not working at high resolution on T1.0 version of +the SoC, giving the following error: +mxc_sdc_fb fb.27: timeout when waiting for flip irq + +Signed-off-by: Gary Bisson +--- + arch/arm/mach-imx/clk-imx6q.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c +index e09b1e8..1e5c410 100644 +--- a/arch/arm/mach-imx/clk-imx6q.c ++++ b/arch/arm/mach-imx/clk-imx6q.c +@@ -279,7 +279,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) + post_div_table[1].div = 1; + post_div_table[2].div = 1; + video_div_table[1].div = 1; +- video_div_table[2].div = 1; ++ video_div_table[3].div = 1; + }; + + /* type name parent_name base div_mask */ +-- +2.1.3 + diff --git a/recipes-kernel/linux/linux-imx_3.10.17.bb b/recipes-kernel/linux/linux-imx_3.10.17.bb index cae1489..143eaab 100644 --- a/recipes-kernel/linux/linux-imx_3.10.17.bb +++ b/recipes-kernel/linux/linux-imx_3.10.17.bb @@ -15,4 +15,6 @@ SRCBRANCH = "imx_3.10.17_1.0.0_ga" SRCREV = "33597e348b2d60dd5c71890ef7b7d3d3fd6e4e97" LOCALVERSION = "-1.0.2_ga" +SRC_URI += "file://0001-ARM-clk-imx6q-fix-video-divider-for-revision-1.0-of-.patch" + COMPATIBLE_MACHINE = "(mx6)" -- 2.1.3