From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9E915CCF2C4 for ; Sat, 17 Oct 2026 23:39:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=54Oa68ZttYbsy84q6dSmnzU6XS51ub6JYC4Sw+aE2vg=; b=vrq40efREHCKf4 J9WAqIcHb4RWIb8ZbgN4+adM5IQ809DU325TsfI1IoK3SREhNoIJAyRdm9/5o3HULEK2ABq+7yE7P GcUU122oEqbtPt0lRqcFzAudndBj7q3TZh3K+PazVYEepzrXiIIHcgbXdDu7vM9+1TVVfU+JJLWR7 NiR0ga2LkByyWKplN9cPnst/bDllvLLMBhUEsA39MgVjIx7cilSjvzrnYI3AdJFgu8dzv6VdL24ga bkaig9BNF5wf4PT5D2YHKBvPDBkaS9MhJzXjkJc2Fb6oJbTkVDMbbsgPC345iMa7kMabdFKhCP8eG OLDdlKH/w4z+4hfqS4Vw==; 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charset="us-ascii"; Format="flowed" Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On 17/10/2026 18:13, Nihal Kumar Gupta wrote: > George posted a C-PHY series [1] which we are currently reviewing. > As discussed with Bryan, this series shares our independent > implementation so the approaches can be compared. > > Two aspects covered here are not in [1]: > > - Settle count calculation derived from sensor-reported T_PREPARE and > T_PREAMBLE timing via get_mbus_config(). [1] left this as an open > question. > > - Data rate based register sequence selection using effective bit > rate (link_freq * 32 / 7). [1] noted downstream does this but > deferred it; this series implements it. > > MIPI CSI-2 operates over two physical layer variants. D-PHY uses a > dedicated differential clock lane with up to four data lanes. C-PHY > encodes the clock within the data stream across up to three wire > trios, eliminating the dedicated clock lane. > > Patch 1 extends the generic PHY framework with PHY_MODE_MIPI_CPHY > and struct phy_configure_opts_mipi_cphy. > > Patch 2 adds t_prepare_ns and t_preamble_ns fields to the CSI-2 > media bus configuration and extends CAMSS to forward them to the PHY > provider for settle count calculation. Sensor drivers must implement > get_mbus_config() and return non-zero values in nanoseconds; stream-on > returns -EINVAL otherwise. The strictness is deliberate: C-PHY settle > timing is symbol-rate-range specific and no safe value can be derived > from link frequency alone. A conservative fallback could be added if > reviewers prefer. > > Patches 3-6 extend the Qualcomm CSIPHY driver: refactor D-PHY > register storage to accommodate C-PHY, accept C-PHY mode with > multiple data rate table selection, compute settle count, and add > lane power mask support for C-PHY trios. > > C-PHY encodes 16 bits per 7 symbols, so the effective bit rate is: > > bit_rate = link_freq * 2 * 16 / 7 = link_freq * 32 / 7 > > where link_freq is symbol_rate / 2 as reported by the sensor via > get_mbus_config(). The rate-table entry whose bandwidth first meets > or exceeds bit_rate is selected. > > The settle count defines how many timer clock cycles the CSIPHY > receiver waits before scanning for C-PHY sync. It is computed from > the sensor's T_PREPARE and T_PREAMBLE timing. The /3 factor reflects > that C-PHY distributes the preamble sequence across three trios: > > settle_cnt = (t_prepare_ns + t_preamble_ns / 3) * timer_clk_rate / 1e9 > > D-PHY settle count is unchanged from before this series. > > [1] https://lore.kernel.org/all/20261016-x1e-cphy-rfc-v3-0-40a346a72153@gmail.com/ > > Signed-off-by: Nihal Kumar Gupta > --- > Nihal Kumar Gupta (6): > phy: core: Add MIPI C-PHY configurations > media: qcom: camss: Add C-PHY timing fields and get config from sensor > phy: qcom: mipi-csi2: Split D-PHY register settings > phy: qcom: mipi-csi2: Accept C-PHY mode and add register sequence > phy: qcom: mipi-csi2: Add C-PHY settle calculation > phy: qcom: mipi-csi2: Add lane mask calculation for C-PHY > > drivers/media/platform/qcom/camss/camss-csiphy.c | 90 +++++++++--- > drivers/media/platform/qcom/camss/camss-csiphy.h | 2 + > drivers/media/platform/qcom/camss/camss.c | 8 +- > drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 159 +++++++++++++++++---- So on thing I notice about this series and like is that there's a small change to the existing 3ph-dphy.c - Since it supports 3ph-cphy the file should be renamed 3ph-cphy-dphy.c (or something) - I like the progressive nature of he changes in this series as structurally the right way to add stuff in. Small digestable commits - I think the missing piece here is data_lanes[] and lane_polarities[] per the other series from Qcom - Another thing is the other series from Anusha has a more advanced mipi_ops data-structure for CPHY. Basically I like the approach taken in this series for a smaller change to the phy-qcom-mipi-csi2-3ph-dphy.c file. I'd like the best of both series - I think there is alot to resolve on lanes, data-lanes and lane-polarities in the other series and looking at this series, it seems to me we don't need a separate phy-qcom-mipi-csi2-3ph-cphy.c, I think Konrad observed in George's series that really the file deals with 3-phase PHYs and that seems true enough. Please work out between yourself and Anusha what's next. If possible I would prefer to contain 3ph CPHY and DPHY to one file as is done here - at the same time the definition of CPHY ops and lane mappings is closer to the spec in the other series. I think either you should take Anusha's structs and lane definitions or Anusha should take your approach to minimal change to the phy-qcom-mipi-csi2-3ph-dphy.c renaming it. One of you needs to pick up the patches from the other one. George can land his stuff on top then. > drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c | 51 +++++-- > drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 25 +++- > include/linux/phy/phy.h | 47 ++++++ > include/media/v4l2-mediabus.h | 2 + > 8 files changed, 315 insertions(+), 69 deletions(-) > --- > base-commit: 2efb7a11f1aa4d2dc285fe2680cca22cb9f72f64 > change-id: 20261017-cphy_support-2ce4d656e631 > > Best regards, > -- > Nihal Kumar Gupta -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3930541A547; Sat, 17 Oct 2026 23:39:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; 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Sat, 17 Oct 2026 23:39:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1792280389; bh=IOaIHN9koYBp4/y2xYG+zvcLw+InozkSxxmt+Azkxmo=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=iToMp5fxLcQH7IgAb1ab5ZzA/49xSXrKI2GQNqawjAqYIk/zQdilaZchaGpGUXlpv iYVY2foBiUqm6ppbXT44B155SUq/sfsyHOI2IF2uhXX8DaSWqzvA5NpAoeY7pH/MIq hBRSPbNlhDPGyFPnn2tDPuud6lnp834DxZWuA2jiuMctz9Hfp/cfxDH6O2oLVNS7+z Ae5vhLDhY2NiNdvzMT2VmN0PkXCAguJTTt0tiGa7NnW5otNE3k8r/TXQfcVMnnWXK2 SuKA7ZILgPurFQT2VsS6CM8lMMXpplyliduQaufxE+dmoIl684vGIpQxlxz/GSh26E 0RxHFbBLFfw/Q== Message-ID: <141c5032-1915-4dac-bbcf-e697b762ae40@kernel.org> Date: Sun, 18 Oct 2026 00:39:45 +0100 Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC 0/6] phy/media: Add generic MIPI C-PHY support to CSI-2 stack To: Nihal Kumar Gupta , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab Cc: Vikram Sharma , linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20261017-cphy_support-v1-0-8b0e1237ce95@oss.qualcomm.com> From: Bryan O'Donoghue Content-Language: en-GB Autocrypt: addr=bod@kernel.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 17/10/2026 18:13, Nihal Kumar Gupta wrote: > George posted a C-PHY series [1] which we are currently reviewing. > As discussed with Bryan, this series shares our independent > implementation so the approaches can be compared. > > Two aspects covered here are not in [1]: > > - Settle count calculation derived from sensor-reported T_PREPARE and > T_PREAMBLE timing via get_mbus_config(). [1] left this as an open > question. > > - Data rate based register sequence selection using effective bit > rate (link_freq * 32 / 7). [1] noted downstream does this but > deferred it; this series implements it. > > MIPI CSI-2 operates over two physical layer variants. D-PHY uses a > dedicated differential clock lane with up to four data lanes. C-PHY > encodes the clock within the data stream across up to three wire > trios, eliminating the dedicated clock lane. > > Patch 1 extends the generic PHY framework with PHY_MODE_MIPI_CPHY > and struct phy_configure_opts_mipi_cphy. > > Patch 2 adds t_prepare_ns and t_preamble_ns fields to the CSI-2 > media bus configuration and extends CAMSS to forward them to the PHY > provider for settle count calculation. Sensor drivers must implement > get_mbus_config() and return non-zero values in nanoseconds; stream-on > returns -EINVAL otherwise. The strictness is deliberate: C-PHY settle > timing is symbol-rate-range specific and no safe value can be derived > from link frequency alone. A conservative fallback could be added if > reviewers prefer. > > Patches 3-6 extend the Qualcomm CSIPHY driver: refactor D-PHY > register storage to accommodate C-PHY, accept C-PHY mode with > multiple data rate table selection, compute settle count, and add > lane power mask support for C-PHY trios. > > C-PHY encodes 16 bits per 7 symbols, so the effective bit rate is: > > bit_rate = link_freq * 2 * 16 / 7 = link_freq * 32 / 7 > > where link_freq is symbol_rate / 2 as reported by the sensor via > get_mbus_config(). The rate-table entry whose bandwidth first meets > or exceeds bit_rate is selected. > > The settle count defines how many timer clock cycles the CSIPHY > receiver waits before scanning for C-PHY sync. It is computed from > the sensor's T_PREPARE and T_PREAMBLE timing. The /3 factor reflects > that C-PHY distributes the preamble sequence across three trios: > > settle_cnt = (t_prepare_ns + t_preamble_ns / 3) * timer_clk_rate / 1e9 > > D-PHY settle count is unchanged from before this series. > > [1] https://lore.kernel.org/all/20261016-x1e-cphy-rfc-v3-0-40a346a72153@gmail.com/ > > Signed-off-by: Nihal Kumar Gupta > --- > Nihal Kumar Gupta (6): > phy: core: Add MIPI C-PHY configurations > media: qcom: camss: Add C-PHY timing fields and get config from sensor > phy: qcom: mipi-csi2: Split D-PHY register settings > phy: qcom: mipi-csi2: Accept C-PHY mode and add register sequence > phy: qcom: mipi-csi2: Add C-PHY settle calculation > phy: qcom: mipi-csi2: Add lane mask calculation for C-PHY > > drivers/media/platform/qcom/camss/camss-csiphy.c | 90 +++++++++--- > drivers/media/platform/qcom/camss/camss-csiphy.h | 2 + > drivers/media/platform/qcom/camss/camss.c | 8 +- > drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 159 +++++++++++++++++---- So on thing I notice about this series and like is that there's a small change to the existing 3ph-dphy.c - Since it supports 3ph-cphy the file should be renamed 3ph-cphy-dphy.c (or something) - I like the progressive nature of he changes in this series as structurally the right way to add stuff in. Small digestable commits - I think the missing piece here is data_lanes[] and lane_polarities[] per the other series from Qcom - Another thing is the other series from Anusha has a more advanced mipi_ops data-structure for CPHY. Basically I like the approach taken in this series for a smaller change to the phy-qcom-mipi-csi2-3ph-dphy.c file. I'd like the best of both series - I think there is alot to resolve on lanes, data-lanes and lane-polarities in the other series and looking at this series, it seems to me we don't need a separate phy-qcom-mipi-csi2-3ph-cphy.c, I think Konrad observed in George's series that really the file deals with 3-phase PHYs and that seems true enough. Please work out between yourself and Anusha what's next. If possible I would prefer to contain 3ph CPHY and DPHY to one file as is done here - at the same time the definition of CPHY ops and lane mappings is closer to the spec in the other series. I think either you should take Anusha's structs and lane definitions or Anusha should take your approach to minimal change to the phy-qcom-mipi-csi2-3ph-dphy.c renaming it. One of you needs to pick up the patches from the other one. George can land his stuff on top then. > drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c | 51 +++++-- > drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 25 +++- > include/linux/phy/phy.h | 47 ++++++ > include/media/v4l2-mediabus.h | 2 + > 8 files changed, 315 insertions(+), 69 deletions(-) > --- > base-commit: 2efb7a11f1aa4d2dc285fe2680cca22cb9f72f64 > change-id: 20261017-cphy_support-2ce4d656e631 > > Best regards, > -- > Nihal Kumar Gupta