From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Subject: Re: [PATCH v2 4/4] PMC driver: Add Cherrytrail PMC interface
Date: Thu, 22 Jan 2015 11:26:10 +0200
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To: "Li, Aubrey" <aubrey.li@linux.intel.com>
Cc: x86@kernel.org, "Rafael J . Wysocki" <rafael.j.wysocki@intel.com>, "Kumar P, Mahesh" <mahesh.kumar.p@intel.com>, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org

On Thu, 2015-01-22 at 12:02 +0800, Li, Aubrey wrote:
> On 2015/1/21 5:50, Andy Shevchenko wrote:
> > The patch adds CHT PMC interface. This exposes all the South IP device power
> > states and S0ix states for CHT. The bit map of FUNC_DIS and D3_STS_0 registers
> > for SoCs are consistent. The D3_STS_1 and FUNC_DIS_2 registers, however, are
> > not aligned. This is fixed by splitting a common mapping on per register basis.
> > 
> Should we define the bit map table completely separate for different
> platforms? My concern is, when D3_STS_0 and FUNC_DIS becomes not
> consistent in a new SoC, the implementation in this patch has to be
> rewritten completely.
> 
> Defining entire bit map table for different platform introduces
> reduplicated bit definitions, but when we add a new platform in future,
> we don't need to consider the existing platforms definition, and no need
> to change code structure any longer.
> 
> Thoughts?
> 

But this what I did by introducing pmc_reg_map structure per SoC.
You may or may not use previous definitions.


-- 
Andy Shevchenko <andriy.shevchenko@intel.com>
Intel Finland Oy