From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: Re: [PATCH v2 04/15] xen/arm: vgic-v3: Correctly handle RAZ/WI registers Date: Mon, 2 Feb 2015 15:27:22 +0000 Message-ID: <1422890842.5838.0.camel@citrix.com> References: <1422555950-31821-1-git-send-email-julien.grall@linaro.org> <1422555950-31821-5-git-send-email-julien.grall@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YIIuQ-0006vT-H4 for xen-devel@lists.xenproject.org; Mon, 02 Feb 2015 15:27:30 +0000 In-Reply-To: <1422555950-31821-5-git-send-email-julien.grall@linaro.org> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Julien Grall Cc: xen-devel@lists.xenproject.org, Vijaya.Kumar@caviumnetworks.com, stefano.stabellini@citrix.com, tim@xen.org List-Id: xen-devel@lists.xenproject.org On Thu, 2015-01-29 at 18:25 +0000, Julien Grall wrote: > Some of the registers are accessible via multiple size (see GICD_IPRIORITYR*). > > Thoses registers are misimplemented when they should be RAZ. Only "Those" and "incorrectly implemented". > word-access size are currently allowed for them. > > To avoid further issues, introduce different label following the access-size > of the registers: > - read_as_zero_64 and write_ignore_64: Used for registers accessible > via a double-word. > - read_as_zero_32 and write_ignore_32: Used for registers accessible > via a word. 5.1.3 suggests there are at least some 64-bit registers where it ought to be possible to read the upper and lower halves independently. BTW, a reference to 5.1.3 in the changelog would be handy. Ian.