From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: Re: [PATCH] xen/arm: Fix rtds scheduler for arm Date: Wed, 4 Feb 2015 15:09:56 +0000 Message-ID: <1423062596.24924.14.camel@citrix.com> References: <54CB8958020000780005B464@mail.emea.novell.com> <1422632449-23130-1-git-send-email-denys.drozdov@globallogic.com> <54CBA76E.4010808@linaro.org> <54CBA9C4.4070305@citrix.com> <54CBAD05.10800@linaro.org> <1422701456.15317.2.camel@citrix.com> <1422875680.10090.4.camel@citrix.com> <54CF7045020000780005BDF7@mail.emea.novell.com> <1422879400.18204.6.camel@citrix.com> <54CF74B7.1050307@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Stefano Stabellini Cc: George Dunlap , Andrew Cooper , Julien Grall , Denys Drozdov , xen-devel@lists.xen.org, Jan Beulich List-Id: xen-devel@lists.xenproject.org On Wed, 2015-02-04 at 15:04 +0000, Stefano Stabellini wrote: > On Mon, 2 Feb 2015, Julien Grall wrote: > > On 02/02/15 12:16, Ian Campbell wrote: > > > On Mon, 2015-02-02 at 11:40 +0000, Jan Beulich wrote: > > >>>>> On 02.02.15 at 12:14, wrote: > > >>> On Mon, 2015-02-02 at 12:49 +0200, Denys Drozdov wrote: > > >>>> The issue observed on credit2 scheduler is similar to the rt scheduler > > >>>> on arm platform. The root cause is that interrupts are disabled in the > > >>>> beginning of arm context_switch, thus spin_lock_irq is failing in > > >>>> ASSERT(local_irq_is_enabled()). I propose to change both credit2 and > > >>>> rt scheduler to run on arm platform as well and re-run the regression > > >>>> with scheduler patches. > > >>> > > >>> I'd like to hear from the scheduler and other $arch folks regarding > > >>> whether we think the rtds and credit2 schedulers are wrong or whether it > > >>> is actually the ARM arch code which needs fixing before considering any > > >>> change. > > >> > > >> The aspect to be understood first is why ARM needs IRQs disabled > > >> past __context_switch() into schedule_tail() (and there until after > > >> ctxt_switch_from() and ctxt_switch_to()). If that's indeed necessary, > > >> there's no question that the schedulers need to be adjusted to > > >> accommodate for this. > > > > > > I don't think it's *necessary*, but we do seem to have ended up with the > > > context switch having that requirement today (and relying on it in > > > several places in switch from/to (mostly to). > > > > > I'm pretty sure we could rework things more along the lines of how x86 > > > does it if needed, but it would be a non-trivial refactoring I think. > > > > We have some part of the code which may inject an interrupt during > > context switch. > > For instance the timer may inject an IRQ as long as it has not been > > disabled. Same when the timer is restored. > > > > The former may result to inject an interrupt to the wrong vCPU. > > Also the gic save and restore functions need to be run with interrupt > disabled. I am aware that today all sorts of things rely on interrupts being disabled during context switch on ARM. My point was that we *could*, if required, rework things to not rely on this. Ian.