From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: Re: [PATCH v2 3/9] xen: arm: Handle 32-bit EL0 on 64-bit EL1 when advancing PC after trap Date: Tue, 10 Feb 2015 06:20:06 +0000 Message-ID: <1423549206.5851.12.camel@citrix.com> References: <1423542956.5851.9.camel@citrix.com> <1423543523-8010-3-git-send-email-ian.campbell@citrix.com> <54D99AA8.4050608@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <54D99AA8.4050608@linaro.org> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Julien Grall Cc: stefano.stabellini@eu.citrix.com, tim@xen.org, xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org On Tue, 2015-02-10 at 13:44 +0800, Julien Grall wrote: > > /* The cond for this instruction works out as the top 4 bits. */ > > - cond = ( it >> 4 ); > > + cond = ( it >> 4 ); > > I haven't spot it in the previous review. This seems to be only a coding > change. Could you specify it in the commit message? Sigh, this level of pedantry isn't really helpful IMHO. Ian.