From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ian Campbell Subject: Re: [PATCH v3 04/15] xen/arm: vgic-v3: Correctly handle RAZ/WI registers Date: Thu, 19 Feb 2015 15:55:23 +0000 Message-ID: <1424361323.30924.100.camel@citrix.com> References: <1424098255-22490-1-git-send-email-julien.grall@linaro.org> <1424098255-22490-5-git-send-email-julien.grall@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YOTS7-0003By-PS for xen-devel@lists.xenproject.org; Thu, 19 Feb 2015 15:55:47 +0000 In-Reply-To: <1424098255-22490-5-git-send-email-julien.grall@linaro.org> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Julien Grall Cc: xen-devel@lists.xenproject.org, Vijaya.Kumar@caviumnetworks.com, tim@xen.org, stefano.stabellini@citrix.com List-Id: xen-devel@lists.xenproject.org On Mon, 2015-02-16 at 14:50 +0000, Julien Grall wrote: > Some of the registers are accessible via multiple size (see GICD_IPRIORITYR*). > > Those registers are incorrectly implemented when they should be RAZ. Only > word-access size are currently allowed for them. > > The paragraph 5.3.1 in the GICv3 spec (PRD03-GENC-010745 24.0) indicates > the different access-sizes supported for each register. > > The current vGICv3 driver is not ready for 32 bits guest and will > require some rework. So, for now, only supporting access-size of a system not > supporting aarch32. > > To avoid further issues, introduce different label following the access-size > of the registers: > - read_as_zero_64 and write_ignore_64: Used for registers accessible > via a double-word. > - read_as_zero_32 and write_ignore_32: Used for registers accessible > via a word. > - read_as_zero: Used when we don't have to check the access size. > > The latter is used when the access size has already been checked in the > register emulation and/or when the register offset is > reserved/implementation defined. > > Signed-off-by: Julien Grall Acked-by: Ian Campbell