From: deepak.s@linux.intel.com
To: intel-gfx@lists.freedesktop.org
Cc: "Satyanantha, Rama Gopal M" <rama.gopal.m.satyanantha@intel.com>
Subject: [RFC] drm/i915: Framebuffers need not be limited to 256MB on gen8+.
Date: Thu, 26 Feb 2015 21:01:52 +0530 [thread overview]
Message-ID: <1424964712-16131-1-git-send-email-deepak.s@linux.intel.com> (raw)
From: Deepak S <deepak.s@linux.intel.com>
The restriction of pinningFramebuffer to first 256MB is removed from gen8+.
Removing the restriction so that FB can be pinned in any space within
GTT/PPGTT. Also, for gen8+ no need to use pin_mappable for Framebuffer &
also we do not take fence as Framebuffer compression is not enabled.
Signed-off-by: Satyanantha, Rama Gopal M <rama.gopal.m.satyanantha@intel.com>
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem.c | 9 +++++++--
drivers/gpu/drm/i915/intel_display.c | 11 +++++++----
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 77a7315..c9f5b06 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3941,6 +3941,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
struct intel_engine_cs *pipelined)
{
u32 old_read_domains, old_write_domain;
+ struct drm_device *dev = obj->base.dev;
bool was_pin_display;
int ret;
@@ -3972,9 +3973,13 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
/* As the user may map the buffer once pinned in the display plane
* (e.g. libkms for the bootup splash), we have to ensure that we
- * always use map_and_fenceable for all scanout buffers.
+ * always use map_and_fenceable for all scanout buffers. No need
+ * of map_fenceable for >= gen8
*/
- ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
+ if ((INTEL_INFO(dev)->gen >= 8))
+ ret = i915_gem_obj_ggtt_pin(obj, alignment, 0);
+ else
+ ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
if (ret)
goto err_unpin_display;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fad5f76..d3067be 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2267,11 +2267,14 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
/* Install a fence for tiled scan-out. Pre-i965 always needs a
* fence, whereas 965+ only requires a fence if using
* framebuffer compression. For simplicity, we always install
- * a fence as the cost is not that onerous.
+ * a fence as the cost is not that onerous. Fence is only required
+ * for gen 7 & below
*/
- ret = i915_gem_object_get_fence(obj);
- if (ret)
- goto err_unpin;
+ if ((INTEL_INFO(dev)->gen <= 7)) {
+ ret = i915_gem_object_get_fence(obj);
+ if (ret)
+ goto err_unpin;
+ }
i915_gem_object_pin_fence(obj);
--
1.9.1
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next reply other threads:[~2015-02-26 15:35 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-26 15:31 deepak.s [this message]
2015-02-26 16:01 ` [RFC] drm/i915: Framebuffers need not be limited to 256MB on gen8+ Chris Wilson
2015-02-26 16:14 ` Damien Lespiau
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