From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephane Viau Subject: [PATCH 2/4] drm/msm/mdp5: Enhance operation mode for pipeline configuration Date: Tue, 3 Mar 2015 13:36:13 -0500 Message-ID: <1425407775-7704-3-git-send-email-sviau@codeaurora.org> References: <1425407775-7704-1-git-send-email-sviau@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1425407775-7704-1-git-send-email-sviau@codeaurora.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org RFNJIGFuZCBXQiBpbnRlcmZhY2VzIG5lZWQgYSBtb3JlIGNvbXBsZXggcGlwZWxpbmUgY29uZmln dXJhdGlvbgp0aGFuIHRoZSBjdXJyZW50IG1kcDVfY3RsX3NldF9pbnRmKCkuCgpGb3IgZXhhbXBs ZSwgbWVtb3J5IG91dHB1dCBjb25uZWN0aW9ucyBuZWVkIHRvIGJlIHNlbGVjdGVkIGZvcgpXQi4g SW50ZXJmYWNlIG1vZGUgKFZpZGVvIHZzLiBDb21tYW5kIG1vZGVzKSBhbHNvIG5lZWQgdG8gYmUK Y29uZmlndXJlZCBmb3IgRFNJLgoKVGhpcyBjaGFuZ2UgdGFrZXMgY2FyZSBvZiBjb25maWd1cmlu ZyB0aGUgd2hvbGUgcGlwZWxpbmUgYXMgZmFyCmFzIG9wZXJhdGlvbiBtb2RlIGdvZXMuIERTSSBh bmQgV0IgaW50ZXJmYWNlcyB3aWxsIGJlIGFkZGVkCmxhdGVyLgoKU2lnbmVkLW9mZi1ieTogU3Rl cGhhbmUgVmlhdSA8c3ZpYXVAY29kZWF1cm9yYS5vcmc+Ci0tLQogZHJpdmVycy9ncHUvZHJtL21z bS9tZHAvbWRwNS9tZHA1X2NmZy5oICAgICB8ICAyICsKIGRyaXZlcnMvZ3B1L2RybS9tc20vbWRw L21kcDUvbWRwNV9jcnRjLmMgICAgfCAzOSArKy0tLS0tLS0tLS0tCiBkcml2ZXJzL2dwdS9kcm0v bXNtL21kcC9tZHA1L21kcDVfY3RsLmMgICAgIHwgOTEgKysrKysrKysrKysrKysrKysrKysrKysr Ky0tLS0KIGRyaXZlcnMvZ3B1L2RybS9tc20vbWRwL21kcDUvbWRwNV9jdGwuaCAgICAgfCAgMyAr LQogZHJpdmVycy9ncHUvZHJtL21zbS9tZHAvbWRwNS9tZHA1X2VuY29kZXIuYyB8IDI5ICsrKysr LS0tLQogZHJpdmVycy9ncHUvZHJtL21zbS9tZHAvbWRwNS9tZHA1X2ttcy5jICAgICB8IDE2ICsr KystCiBkcml2ZXJzL2dwdS9kcm0vbXNtL21kcC9tZHA1L21kcDVfa21zLmggICAgIHwgNDggKysr KysrKysrKysrLS0tCiA3IGZpbGVzIGNoYW5nZWQsIDE1NyBpbnNlcnRpb25zKCspLCA3MSBkZWxl dGlvbnMoLSkKCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vbXNtL21kcC9tZHA1L21kcDVf Y2ZnLmggYi9kcml2ZXJzL2dwdS9kcm0vbXNtL21kcC9tZHA1L21kcDVfY2ZnLmgKaW5kZXggZGJh NGQ1Mi4uYmU1ODdiOCAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL21zbS9tZHAvbWRwNS9t ZHA1X2NmZy5oCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9tc20vbWRwL21kcDUvbWRwNV9jZmcuaApA QCAtMzEsNiArMzEsOCBAQCBleHRlcm4gY29uc3Qgc3RydWN0IG1kcDVfY2ZnX2h3ICptZHA1X2Nm ZzsKIAogdHlwZWRlZiBERUNMQVJFX0JJVE1BUChtZHA1X3NtcF9zdGF0ZV90LCBNQVhfU01QX0JM T0NLUyk7CiAKKyNkZWZpbmUgTURQNV9JTlRGX0lTX1ZJUlRVQUxfRElTUExBWShpbnRmX3R5cGUp ICAgKChpbnRmX3R5cGUpID49IElOVEZfVklSVFVBTCkKKwogI2RlZmluZSBNRFA1X1NVQl9CTE9D S19ERUZJTklUSU9OIFwKIAlpbnQgY291bnQ7IFwKIAl1aW50MzJfdCBiYXNlW01BWF9CQVNFU10K ZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tc20vbWRwL21kcDUvbWRwNV9jcnRjLmMgYi9k cml2ZXJzL2dwdS9kcm0vbXNtL21kcC9tZHA1L21kcDVfY3J0Yy5jCmluZGV4IGJmYmEyMzYuLjE1 MTM2ZjEgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tc20vbWRwL21kcDUvbWRwNV9jcnRj LmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL21zbS9tZHAvbWRwNS9tZHA1X2NydGMuYwpAQCAtNjEx LDQ4ICs2MTEsMTcgQEAgdm9pZCBtZHA1X2NydGNfY2FuY2VsX3BlbmRpbmdfZmxpcChzdHJ1Y3Qg ZHJtX2NydGMgKmNydGMsIHN0cnVjdCBkcm1fZmlsZSAqZmlsZSkKIH0KIAogLyogc2V0IGludGVy ZmFjZSBmb3Igcm91dGluZyBjcnRjLT5lbmNvZGVyOiAqLwotdm9pZCBtZHA1X2NydGNfc2V0X2lu dGYoc3RydWN0IGRybV9jcnRjICpjcnRjLCBpbnQgaW50ZiwKLQkJZW51bSBtZHA1X2ludGYgaW50 Zl9pZCkKK3ZvaWQgbWRwNV9jcnRjX3NldF9pbnRmKHN0cnVjdCBkcm1fY3J0YyAqY3J0Yywgc3Ry dWN0IG1kcDVfaW50ZXJmYWNlICppbnRmKQogewogCXN0cnVjdCBtZHA1X2NydGMgKm1kcDVfY3J0 YyA9IHRvX21kcDVfY3J0YyhjcnRjKTsKIAlzdHJ1Y3QgbWRwNV9rbXMgKm1kcDVfa21zID0gZ2V0 X2ttcyhjcnRjKTsKLQl1aW50MzJfdCBpbnRmX3NlbDsKLQl1bnNpZ25lZCBsb25nIGZsYWdzOwor CWludCBsbSA9IG1kcDVfY3J0Y19nZXRfbG0oY3J0Yyk7CiAKIAkvKiBub3cgdGhhdCB3ZSBrbm93 IHdoYXQgaXJxJ3Mgd2Ugd2FudDogKi8KLQltZHA1X2NydGMtPmVyci5pcnFtYXNrID0gaW50ZjJl cnIoaW50Zik7Ci0JbWRwNV9jcnRjLT52YmxhbmsuaXJxbWFzayA9IGludGYydmJsYW5rKGludGYp OworCW1kcDVfY3J0Yy0+ZXJyLmlycW1hc2sgPSBpbnRmMmVycihpbnRmLT5udW0pOworCW1kcDVf Y3J0Yy0+dmJsYW5rLmlycW1hc2sgPSBpbnRmMnZibGFuayhsbSwgaW50Zik7CiAJbWRwX2lycV91 cGRhdGUoJm1kcDVfa21zLT5iYXNlKTsKIAotCXNwaW5fbG9ja19pcnFzYXZlKCZtZHA1X2ttcy0+ cmVzb3VyY2VfbG9jaywgZmxhZ3MpOwotCWludGZfc2VsID0gbWRwNV9yZWFkKG1kcDVfa21zLCBS RUdfTURQNV9ESVNQX0lOVEZfU0VMKTsKLQotCXN3aXRjaCAoaW50ZikgewotCWNhc2UgMDoKLQkJ aW50Zl9zZWwgJj0gfk1EUDVfRElTUF9JTlRGX1NFTF9JTlRGMF9fTUFTSzsKLQkJaW50Zl9zZWwg fD0gTURQNV9ESVNQX0lOVEZfU0VMX0lOVEYwKGludGZfaWQpOwotCQlicmVhazsKLQljYXNlIDE6 Ci0JCWludGZfc2VsICY9IH5NRFA1X0RJU1BfSU5URl9TRUxfSU5URjFfX01BU0s7Ci0JCWludGZf c2VsIHw9IE1EUDVfRElTUF9JTlRGX1NFTF9JTlRGMShpbnRmX2lkKTsKLQkJYnJlYWs7Ci0JY2Fz ZSAyOgotCQlpbnRmX3NlbCAmPSB+TURQNV9ESVNQX0lOVEZfU0VMX0lOVEYyX19NQVNLOwotCQlp bnRmX3NlbCB8PSBNRFA1X0RJU1BfSU5URl9TRUxfSU5URjIoaW50Zl9pZCk7Ci0JCWJyZWFrOwot CWNhc2UgMzoKLQkJaW50Zl9zZWwgJj0gfk1EUDVfRElTUF9JTlRGX1NFTF9JTlRGM19fTUFTSzsK LQkJaW50Zl9zZWwgfD0gTURQNV9ESVNQX0lOVEZfU0VMX0lOVEYzKGludGZfaWQpOwotCQlicmVh azsKLQlkZWZhdWx0OgotCQlCVUcoKTsKLQkJYnJlYWs7Ci0JfQotCi0JbWRwNV93cml0ZShtZHA1 X2ttcywgUkVHX01EUDVfRElTUF9JTlRGX1NFTCwgaW50Zl9zZWwpOwotCXNwaW5fdW5sb2NrX2ly cXJlc3RvcmUoJm1kcDVfa21zLT5yZXNvdXJjZV9sb2NrLCBmbGFncyk7Ci0KLQlEQkcoIiVzOiBp bnRmX3NlbD0lMDh4IiwgbWRwNV9jcnRjLT5uYW1lLCBpbnRmX3NlbCk7CiAJbWRwNV9jdGxfc2V0 X2ludGYobWRwNV9jcnRjLT5jdGwsIGludGYpOwogfQogCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dw dS9kcm0vbXNtL21kcC9tZHA1L21kcDVfY3RsLmMgYi9kcml2ZXJzL2dwdS9kcm0vbXNtL21kcC9t ZHA1L21kcDVfY3RsLmMKaW5kZXggMTUxMTI5MC4uM2U4OGJiNyAxMDA2NDQKLS0tIGEvZHJpdmVy cy9ncHUvZHJtL21zbS9tZHAvbWRwNS9tZHA1X2N0bC5jCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9t c20vbWRwL21kcDUvbWRwNV9jdGwuYwpAQCAtMzMsNiArMzMsMTYgQEAKICAqIHJlcXVlc3RlZCBi eSB0aGUgY2xpZW50IChpbiBtZHA1X2NydGNfbW9kZV9zZXQoKSkuCiAgKi8KIAorc3RydWN0IG9w X21vZGUgeworCXN0cnVjdCBtZHA1X2ludGVyZmFjZSBpbnRmOworCS8qCisJICogVE9ETzogYWRk IGEgc3RhdGUgdmFyaWFibGUgdG8gY29udHJvbCB0aGUgcGlwZWxpbmUKKwkgKgorCSAqIGVnOiBX QiBpbnRlcmZhY2UgbmVlZHMgYm90aCBidWZmZXIgYWRkcmVzc2VzIHRvIGJlIGNvbW1pdHRlZCAr CisJICogb3V0cHV0IGJ1ZmZlcnMgcmVhZHkgdG8gYmUgd3JpdHRlbiBpbnRvLCBiZWZvcmUgd2Ug Y2FuIFNUQVJULgorCSAqLworfTsKKwogc3RydWN0IG1kcDVfY3RsIHsKIAlzdHJ1Y3QgbWRwNV9j dGxfbWFuYWdlciAqY3RsbTsKIApAQCAtNDEsOCArNTEsOCBAQCBzdHJ1Y3QgbWRwNV9jdGwgewog CS8qIHdoZXRoZXIgdGhpcyBDVEwgaGFzIGJlZW4gYWxsb2NhdGVkIG9yIG5vdDogKi8KIAlib29s IGJ1c3k7CiAKLQkvKiBtZW1vcnkgb3V0cHV0IGNvbm5lY3Rpb24gKEBzZWUgbWRwNV9jdGxfbW9k ZSk6ICovCi0JdTMyIG1vZGU7CisJLyogT3BlcmF0aW9uIE1vZGUgQ29uZmlndXJhdGlvbiBmb3Ig dGhlIFBpcGVsaW5lICovCisJc3RydWN0IG9wX21vZGUgcGlwZWxpbmU7CiAKIAkvKiBSRUdfTURQ NV9DVExfKig8aWQ+KSByZWdpc3RlcnMgYWNjZXNzIGluZm8gKyBsb2NrOiAqLwogCXNwaW5sb2Nr X3QgaHdfbG9jazsKQEAgLTk0LDE5ICsxMDQsODEgQEAgdTMyIGN0bF9yZWFkKHN0cnVjdCBtZHA1 X2N0bCAqY3RsLCB1MzIgcmVnKQogCXJldHVybiBtZHA1X3JlYWQobWRwNV9rbXMsIHJlZyk7CiB9 CiAKK3N0YXRpYyB2b2lkIHNldF9kaXNwbGF5X2ludGYoc3RydWN0IG1kcDVfa21zICptZHA1X2tt cywKKwkJc3RydWN0IG1kcDVfaW50ZXJmYWNlICppbnRmKQoreworCXVuc2lnbmVkIGxvbmcgZmxh Z3M7CisJdTMyIGludGZfc2VsOworCisJc3Bpbl9sb2NrX2lycXNhdmUoJm1kcDVfa21zLT5yZXNv dXJjZV9sb2NrLCBmbGFncyk7CisJaW50Zl9zZWwgPSBtZHA1X3JlYWQobWRwNV9rbXMsIFJFR19N RFA1X0RJU1BfSU5URl9TRUwpOworCisJc3dpdGNoIChpbnRmLT5udW0pIHsKKwljYXNlIDA6CisJ CWludGZfc2VsICY9IH5NRFA1X0RJU1BfSU5URl9TRUxfSU5URjBfX01BU0s7CisJCWludGZfc2Vs IHw9IE1EUDVfRElTUF9JTlRGX1NFTF9JTlRGMChpbnRmLT50eXBlKTsKKwkJYnJlYWs7CisJY2Fz ZSAxOgorCQlpbnRmX3NlbCAmPSB+TURQNV9ESVNQX0lOVEZfU0VMX0lOVEYxX19NQVNLOworCQlp bnRmX3NlbCB8PSBNRFA1X0RJU1BfSU5URl9TRUxfSU5URjEoaW50Zi0+dHlwZSk7CisJCWJyZWFr OworCWNhc2UgMjoKKwkJaW50Zl9zZWwgJj0gfk1EUDVfRElTUF9JTlRGX1NFTF9JTlRGMl9fTUFT SzsKKwkJaW50Zl9zZWwgfD0gTURQNV9ESVNQX0lOVEZfU0VMX0lOVEYyKGludGYtPnR5cGUpOwor CQlicmVhazsKKwljYXNlIDM6CisJCWludGZfc2VsICY9IH5NRFA1X0RJU1BfSU5URl9TRUxfSU5U RjNfX01BU0s7CisJCWludGZfc2VsIHw9IE1EUDVfRElTUF9JTlRGX1NFTF9JTlRGMyhpbnRmLT50 eXBlKTsKKwkJYnJlYWs7CisJZGVmYXVsdDoKKwkJQlVHKCk7CisJCWJyZWFrOworCX0KKworCW1k cDVfd3JpdGUobWRwNV9rbXMsIFJFR19NRFA1X0RJU1BfSU5URl9TRUwsIGludGZfc2VsKTsKKwlz cGluX3VubG9ja19pcnFyZXN0b3JlKCZtZHA1X2ttcy0+cmVzb3VyY2VfbG9jaywgZmxhZ3MpOwor fQogCi1pbnQgbWRwNV9jdGxfc2V0X2ludGYoc3RydWN0IG1kcDVfY3RsICpjdGwsIGludCBpbnRm KQorc3RhdGljIHZvaWQgc2V0X2N0bF9vcChzdHJ1Y3QgbWRwNV9jdGwgKmN0bCwgc3RydWN0IG1k cDVfaW50ZXJmYWNlICppbnRmKQogewogCXVuc2lnbmVkIGxvbmcgZmxhZ3M7Ci0Jc3RhdGljIGNv bnN0IGVudW0gbWRwNV9pbnRmbnVtIGludGZudW1bXSA9IHsKLQkJCUlOVEYwLCBJTlRGMSwgSU5U RjIsIElOVEYzLAotCX07CisJdTMyIGN0bF9vcCA9IDA7CisKKwlpZiAoIU1EUDVfSU5URl9JU19W SVJUVUFMX0RJU1BMQVkoaW50Zi0+dHlwZSkpCisJCWN0bF9vcCB8PSBNRFA1X0NUTF9PUF9JTlRG X05VTShJTlRGMCArIGludGYtPm51bSk7CisKKwlzd2l0Y2ggKGludGYtPnR5cGUpIHsKKwljYXNl IElOVEZfRFNJOgorCQlpZiAoaW50Zi0+bW9kZSA9PSBNRFA1X0lOVEZfRFNJX01PREVfQ09NTUFO RCkKKwkJCWN0bF9vcCB8PSBNRFA1X0NUTF9PUF9DTURfTU9ERTsKKwkJYnJlYWs7CisKKwljYXNl IElOVEZfV0I6CisJCWlmIChpbnRmLT5tb2RlID09IE1EUDVfSU5URl9XQl9NT0RFX0xJTkUpCisJ CQljdGxfb3AgfD0gTURQNV9DVExfT1BfTU9ERShNT0RFX1dCXzJfTElORSk7CisJCWJyZWFrOwor CisJZGVmYXVsdDoKKwkJYnJlYWs7CisJfQogCiAJc3Bpbl9sb2NrX2lycXNhdmUoJmN0bC0+aHdf bG9jaywgZmxhZ3MpOwotCWN0bF93cml0ZShjdGwsIFJFR19NRFA1X0NUTF9PUChjdGwtPmlkKSwK LQkJCU1EUDVfQ1RMX09QX01PREUoY3RsLT5tb2RlKSB8Ci0JCQlNRFA1X0NUTF9PUF9JTlRGX05V TShpbnRmbnVtW2ludGZdKSk7CisJY3RsX3dyaXRlKGN0bCwgUkVHX01EUDVfQ1RMX09QKGN0bC0+ aWQpLCBjdGxfb3ApOwogCXNwaW5fdW5sb2NrX2lycXJlc3RvcmUoJmN0bC0+aHdfbG9jaywgZmxh Z3MpOworfQorCitpbnQgbWRwNV9jdGxfc2V0X2ludGYoc3RydWN0IG1kcDVfY3RsICpjdGwsIHN0 cnVjdCBtZHA1X2ludGVyZmFjZSAqaW50ZikKK3sKKwlzdHJ1Y3QgbWRwNV9jdGxfbWFuYWdlciAq Y3RsX21nciA9IGN0bC0+Y3RsbTsKKwlzdHJ1Y3QgbWRwNV9rbXMgKm1kcDVfa21zID0gZ2V0X2tt cyhjdGxfbWdyKTsKKworCW1lbWNweSgmY3RsLT5waXBlbGluZS5pbnRmLCBpbnRmLCBzaXplb2Yo KmludGYpKTsKKworCS8qIFZpcnR1YWwgaW50ZXJmYWNlcyBuZWVkIG5vdCBzZXQgYSBkaXNwbGF5 IGludGYgKGUuZy46IFdyaXRlYmFjaykgKi8KKwlpZiAoIU1EUDVfSU5URl9JU19WSVJUVUFMX0RJ U1BMQVkoaW50Zi0+dHlwZSkpCisJCXNldF9kaXNwbGF5X2ludGYobWRwNV9rbXMsIGludGYpOwor CisJc2V0X2N0bF9vcChjdGwsIGludGYpOwogCiAJcmV0dXJuIDA7CiB9CkBAIC0zMDMsNyArMzc1 LDYgQEAgc3RydWN0IG1kcDVfY3RsX21hbmFnZXIgKm1kcDVfY3RsbV9pbml0KHN0cnVjdCBkcm1f ZGV2aWNlICpkZXYsCiAJCX0KIAkJY3RsLT5jdGxtID0gY3RsX21ncjsKIAkJY3RsLT5pZCA9IGM7 Ci0JCWN0bC0+bW9kZSA9IE1PREVfTk9ORTsKIAkJY3RsLT5yZWdfb2Zmc2V0ID0gY3RsX2NmZy0+ YmFzZVtjXTsKIAkJY3RsLT5mbHVzaF9tYXNrID0gTURQNV9DVExfRkxVU0hfQ1RMOwogCQljdGwt PmJ1c3kgPSBmYWxzZTsKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tc20vbWRwL21kcDUv bWRwNV9jdGwuaCBiL2RyaXZlcnMvZ3B1L2RybS9tc20vbWRwL21kcDUvbWRwNV9jdGwuaAppbmRl eCBhZDQ4Nzg4Li4yNzFkNWFjIDEwMDY0NAotLS0gYS9kcml2ZXJzL2dwdS9kcm0vbXNtL21kcC9t ZHA1L21kcDVfY3RsLmgKKysrIGIvZHJpdmVycy9ncHUvZHJtL21zbS9tZHAvbWRwNS9tZHA1X2N0 bC5oCkBAIC0zNCw3ICszNCw4IEBAIHZvaWQgbWRwNV9jdGxtX2Rlc3Ryb3koc3RydWN0IG1kcDVf Y3RsX21hbmFnZXIgKmN0bG0pOwogICovCiBzdHJ1Y3QgbWRwNV9jdGwgKm1kcDVfY3RsbV9yZXF1 ZXN0KHN0cnVjdCBtZHA1X2N0bF9tYW5hZ2VyICpjdGxtLCBzdHJ1Y3QgZHJtX2NydGMgKmNydGMp OwogCi1pbnQgbWRwNV9jdGxfc2V0X2ludGYoc3RydWN0IG1kcDVfY3RsICpjdGwsIGludCBpbnRm KTsKK3N0cnVjdCBtZHA1X2ludGVyZmFjZTsKK2ludCBtZHA1X2N0bF9zZXRfaW50ZihzdHJ1Y3Qg bWRwNV9jdGwgKmN0bCwgc3RydWN0IG1kcDVfaW50ZXJmYWNlICppbnRmKTsKIAogaW50IG1kcDVf Y3RsX3NldF9jdXJzb3Ioc3RydWN0IG1kcDVfY3RsICpjdGwsIGJvb2wgZW5hYmxlKTsKIApkaWZm IC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21zbS9tZHAvbWRwNS9tZHA1X2VuY29kZXIuYyBiL2Ry aXZlcnMvZ3B1L2RybS9tc20vbWRwL21kcDUvbWRwNV9lbmNvZGVyLmMKaW5kZXggYTA5ZmE1OC4u ZjNiNmZlOCAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL21zbS9tZHAvbWRwNS9tZHA1X2Vu Y29kZXIuYworKysgYi9kcml2ZXJzL2dwdS9kcm0vbXNtL21kcC9tZHA1L21kcDVfZW5jb2Rlci5j CkBAIC0yMyw4ICsyMyw3IEBACiAKIHN0cnVjdCBtZHA1X2VuY29kZXIgewogCXN0cnVjdCBkcm1f ZW5jb2RlciBiYXNlOwotCWludCBpbnRmOwotCWVudW0gbWRwNV9pbnRmIGludGZfaWQ7CisJc3Ry dWN0IG1kcDVfaW50ZXJmYWNlIGludGY7CiAJc3BpbmxvY2tfdCBpbnRmX2xvY2s7CS8qIHByb3Rl Y3QgUkVHX01EUDVfSU5URl8qIHJlZ2lzdGVycyAqLwogCWJvb2wgZW5hYmxlZDsKIAl1aW50MzJf dCBic2M7CkBAIC0xMjYsNyArMTI1LDcgQEAgc3RhdGljIHZvaWQgbWRwNV9lbmNvZGVyX21vZGVf c2V0KHN0cnVjdCBkcm1fZW5jb2RlciAqZW5jb2RlciwKIAlzdHJ1Y3QgbWRwNV9rbXMgKm1kcDVf a21zID0gZ2V0X2ttcyhlbmNvZGVyKTsKIAlzdHJ1Y3QgZHJtX2RldmljZSAqZGV2ID0gZW5jb2Rl ci0+ZGV2OwogCXN0cnVjdCBkcm1fY29ubmVjdG9yICpjb25uZWN0b3I7Ci0JaW50IGludGYgPSBt ZHA1X2VuY29kZXItPmludGY7CisJaW50IGludGYgPSBtZHA1X2VuY29kZXItPmludGYubnVtOwog CXVpbnQzMl90IGR0dl9oc3luY19za2V3LCB2c3luY19wZXJpb2QsIHZzeW5jX2xlbiwgY3RybF9w b2w7CiAJdWludDMyX3QgZGlzcGxheV92X3N0YXJ0LCBkaXNwbGF5X3ZfZW5kOwogCXVpbnQzMl90 IGhzeW5jX3N0YXJ0X3gsIGhzeW5jX2VuZF94OwpAQCAtMTg4LDcgKzE4Nyw3IEBAIHN0YXRpYyB2 b2lkIG1kcDVfZW5jb2Rlcl9tb2RlX3NldChzdHJ1Y3QgZHJtX2VuY29kZXIgKmVuY29kZXIsCiAJ ICogRElTUExBWV9WX1NUQVJUID0gKFZCUCAqIEhDWUNMRSkgKyBIQlAKIAkgKiBESVNQTEFZX1Zf RU5EID0gKFZCUCArIFZBQ1RJVkUpICogSENZQ0xFIC0gMSAtIEhGUAogCSAqLwotCWlmIChtZHA1 X2VuY29kZXItPmludGZfaWQgPT0gSU5URl9lRFApIHsKKwlpZiAobWRwNV9lbmNvZGVyLT5pbnRm LnR5cGUgPT0gSU5URl9lRFApIHsKIAkJZGlzcGxheV92X3N0YXJ0ICs9IG1vZGUtPmh0b3RhbCAt IG1vZGUtPmhzeW5jX3N0YXJ0OwogCQlkaXNwbGF5X3ZfZW5kIC09IG1vZGUtPmhzeW5jX3N0YXJ0 IC0gbW9kZS0+aGRpc3BsYXk7CiAJfQpAQCAtMjI0LDE0ICsyMjMsMTYgQEAgc3RhdGljIHZvaWQg bWRwNV9lbmNvZGVyX2Rpc2FibGUoc3RydWN0IGRybV9lbmNvZGVyICplbmNvZGVyKQogewogCXN0 cnVjdCBtZHA1X2VuY29kZXIgKm1kcDVfZW5jb2RlciA9IHRvX21kcDVfZW5jb2RlcihlbmNvZGVy KTsKIAlzdHJ1Y3QgbWRwNV9rbXMgKm1kcDVfa21zID0gZ2V0X2ttcyhlbmNvZGVyKTsKLQlpbnQg aW50ZiA9IG1kcDVfZW5jb2Rlci0+aW50ZjsKKwlpbnQgbG0gPSBtZHA1X2NydGNfZ2V0X2xtKGVu Y29kZXItPmNydGMpOworCXN0cnVjdCBtZHA1X2ludGVyZmFjZSAqaW50ZiA9ICZtZHA1X2VuY29k ZXItPmludGY7CisJaW50IGludGZuID0gbWRwNV9lbmNvZGVyLT5pbnRmLm51bTsKIAl1bnNpZ25l ZCBsb25nIGZsYWdzOwogCiAJaWYgKFdBUk5fT04oIW1kcDVfZW5jb2Rlci0+ZW5hYmxlZCkpCiAJ CXJldHVybjsKIAogCXNwaW5fbG9ja19pcnFzYXZlKCZtZHA1X2VuY29kZXItPmludGZfbG9jaywg ZmxhZ3MpOwotCW1kcDVfd3JpdGUobWRwNV9rbXMsIFJFR19NRFA1X0lOVEZfVElNSU5HX0VOR0lO RV9FTihpbnRmKSwgMCk7CisJbWRwNV93cml0ZShtZHA1X2ttcywgUkVHX01EUDVfSU5URl9USU1J TkdfRU5HSU5FX0VOKGludGZuKSwgMCk7CiAJc3Bpbl91bmxvY2tfaXJxcmVzdG9yZSgmbWRwNV9l bmNvZGVyLT5pbnRmX2xvY2ssIGZsYWdzKTsKIAogCS8qCkBAIC0yNDIsNyArMjQzLDcgQEAgc3Rh dGljIHZvaWQgbWRwNV9lbmNvZGVyX2Rpc2FibGUoc3RydWN0IGRybV9lbmNvZGVyICplbmNvZGVy KQogCSAqIHRoZSBzZXR0aW5ncyBjaGFuZ2VzIGZvciB0aGUgbmV3IG1vZGVzZXQgKGxpa2UgbmV3 CiAJICogc2Nhbm91dCBidWZmZXIpIGRvbid0IGxhdGNoIHByb3Blcmx5Li4KIAkgKi8KLQltZHBf aXJxX3dhaXQoJm1kcDVfa21zLT5iYXNlLCBpbnRmMnZibGFuayhpbnRmKSk7CisJbWRwX2lycV93 YWl0KCZtZHA1X2ttcy0+YmFzZSwgaW50ZjJ2YmxhbmsobG0sIGludGYpKTsKIAogCWJzX3NldCht ZHA1X2VuY29kZXIsIDApOwogCkBAIC0yNTMsMTggKzI1NCwxNyBAQCBzdGF0aWMgdm9pZCBtZHA1 X2VuY29kZXJfZW5hYmxlKHN0cnVjdCBkcm1fZW5jb2RlciAqZW5jb2RlcikKIHsKIAlzdHJ1Y3Qg bWRwNV9lbmNvZGVyICptZHA1X2VuY29kZXIgPSB0b19tZHA1X2VuY29kZXIoZW5jb2Rlcik7CiAJ c3RydWN0IG1kcDVfa21zICptZHA1X2ttcyA9IGdldF9rbXMoZW5jb2Rlcik7Ci0JaW50IGludGYg PSBtZHA1X2VuY29kZXItPmludGY7CisJaW50IGludGZuID0gbWRwNV9lbmNvZGVyLT5pbnRmLm51 bTsKIAl1bnNpZ25lZCBsb25nIGZsYWdzOwogCiAJaWYgKFdBUk5fT04obWRwNV9lbmNvZGVyLT5l bmFibGVkKSkKIAkJcmV0dXJuOwogCi0JbWRwNV9jcnRjX3NldF9pbnRmKGVuY29kZXItPmNydGMs IG1kcDVfZW5jb2Rlci0+aW50ZiwKLQkJCW1kcDVfZW5jb2Rlci0+aW50Zl9pZCk7CisJbWRwNV9j cnRjX3NldF9pbnRmKGVuY29kZXItPmNydGMsICZtZHA1X2VuY29kZXItPmludGYpOwogCiAJYnNf c2V0KG1kcDVfZW5jb2RlciwgMSk7CiAJc3Bpbl9sb2NrX2lycXNhdmUoJm1kcDVfZW5jb2Rlci0+ aW50Zl9sb2NrLCBmbGFncyk7Ci0JbWRwNV93cml0ZShtZHA1X2ttcywgUkVHX01EUDVfSU5URl9U SU1JTkdfRU5HSU5FX0VOKGludGYpLCAxKTsKKwltZHA1X3dyaXRlKG1kcDVfa21zLCBSRUdfTURQ NV9JTlRGX1RJTUlOR19FTkdJTkVfRU4oaW50Zm4pLCAxKTsKIAlzcGluX3VubG9ja19pcnFyZXN0 b3JlKCZtZHA1X2VuY29kZXItPmludGZfbG9jaywgZmxhZ3MpOwogCiAJbWRwNV9lbmNvZGVyLT5l bmFibGVkID0gdHJ1ZTsKQEAgLTI3OCw4ICsyNzgsOCBAQCBzdGF0aWMgY29uc3Qgc3RydWN0IGRy bV9lbmNvZGVyX2hlbHBlcl9mdW5jcyBtZHA1X2VuY29kZXJfaGVscGVyX2Z1bmNzID0gewogfTsK IAogLyogaW5pdGlhbGl6ZSBlbmNvZGVyICovCi1zdHJ1Y3QgZHJtX2VuY29kZXIgKm1kcDVfZW5j b2Rlcl9pbml0KHN0cnVjdCBkcm1fZGV2aWNlICpkZXYsIGludCBpbnRmLAotCQllbnVtIG1kcDVf aW50ZiBpbnRmX2lkKQorc3RydWN0IGRybV9lbmNvZGVyICptZHA1X2VuY29kZXJfaW5pdChzdHJ1 Y3QgZHJtX2RldmljZSAqZGV2LAorCQkJCXN0cnVjdCBtZHA1X2ludGVyZmFjZSAqaW50ZikKIHsK IAlzdHJ1Y3QgZHJtX2VuY29kZXIgKmVuY29kZXIgPSBOVUxMOwogCXN0cnVjdCBtZHA1X2VuY29k ZXIgKm1kcDVfZW5jb2RlcjsKQEAgLTI5MSw4ICsyOTEsNyBAQCBzdHJ1Y3QgZHJtX2VuY29kZXIg Km1kcDVfZW5jb2Rlcl9pbml0KHN0cnVjdCBkcm1fZGV2aWNlICpkZXYsIGludCBpbnRmLAogCQln b3RvIGZhaWw7CiAJfQogCi0JbWRwNV9lbmNvZGVyLT5pbnRmID0gaW50ZjsKLQltZHA1X2VuY29k ZXItPmludGZfaWQgPSBpbnRmX2lkOworCW1lbWNweSgmbWRwNV9lbmNvZGVyLT5pbnRmLCBpbnRm LCBzaXplb2YobWRwNV9lbmNvZGVyLT5pbnRmKSk7CiAJZW5jb2RlciA9ICZtZHA1X2VuY29kZXIt PmJhc2U7CiAKIAlzcGluX2xvY2tfaW5pdCgmbWRwNV9lbmNvZGVyLT5pbnRmX2xvY2spOwpkaWZm IC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL21zbS9tZHAvbWRwNS9tZHA1X2ttcy5jIGIvZHJpdmVy cy9ncHUvZHJtL21zbS9tZHAvbWRwNS9tZHA1X2ttcy5jCmluZGV4IDkyYjYxZGIuLjM5MGQ5ZDIg MTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tc20vbWRwL21kcDUvbWRwNV9rbXMuYworKysg Yi9kcml2ZXJzL2dwdS9kcm0vbXNtL21kcC9tZHA1L21kcDVfa21zLmMKQEAgLTIyMyw4ICsyMjMs MTQgQEAgc3RhdGljIGludCBtb2Rlc2V0X2luaXQoc3RydWN0IG1kcDVfa21zICptZHA1X2ttcykK IAl9CiAKIAlpZiAocHJpdi0+aGRtaSkgeworCQlzdHJ1Y3QgbWRwNV9pbnRlcmZhY2UgaW50ZiA9 IHsKKwkJCQkubnVtCT0gMywKKwkJCQkudHlwZQk9IElOVEZfSERNSSwKKwkJCQkubW9kZQk9IE1E UDVfSU5URl9NT0RFX05PTkUsCisJCX07CisKIAkJLyogQ29uc3RydWN0IGVuY29kZXIgZm9yIEhE TUk6ICovCi0JCWVuY29kZXIgPSBtZHA1X2VuY29kZXJfaW5pdChkZXYsIDMsIElOVEZfSERNSSk7 CisJCWVuY29kZXIgPSBtZHA1X2VuY29kZXJfaW5pdChkZXYsICZpbnRmKTsKIAkJaWYgKElTX0VS UihlbmNvZGVyKSkgewogCQkJZGV2X2VycihkZXYtPmRldiwgImZhaWxlZCB0byBjb25zdHJ1Y3Qg ZW5jb2RlclxuIik7CiAJCQlyZXQgPSBQVFJfRVJSKGVuY29kZXIpOwpAQCAtMjQyLDggKzI0OCwx NCBAQCBzdGF0aWMgaW50IG1vZGVzZXRfaW5pdChzdHJ1Y3QgbWRwNV9rbXMgKm1kcDVfa21zKQog CX0KIAogCWlmIChwcml2LT5lZHApIHsKKwkJc3RydWN0IG1kcDVfaW50ZXJmYWNlIGludGYgPSB7 CisJCQkJLm51bQk9IDAsCisJCQkJLnR5cGUJPSBJTlRGX2VEUCwKKwkJCQkubW9kZQk9IE1EUDVf SU5URl9NT0RFX05PTkUsCisJCX07CisKIAkJLyogQ29uc3RydWN0IGVuY29kZXIgZm9yIGVEUDog Ki8KLQkJZW5jb2RlciA9IG1kcDVfZW5jb2Rlcl9pbml0KGRldiwgMCwgSU5URl9lRFApOworCQll bmNvZGVyID0gbWRwNV9lbmNvZGVyX2luaXQoZGV2LCAmaW50Zik7CiAJCWlmIChJU19FUlIoZW5j b2RlcikpIHsKIAkJCWRldl9lcnIoZGV2LT5kZXYsICJmYWlsZWQgdG8gY29uc3RydWN0IGVEUCBl bmNvZGVyXG4iKTsKIAkJCXJldCA9IFBUUl9FUlIoZW5jb2Rlcik7CmRpZmYgLS1naXQgYS9kcml2 ZXJzL2dwdS9kcm0vbXNtL21kcC9tZHA1L21kcDVfa21zLmggYi9kcml2ZXJzL2dwdS9kcm0vbXNt L21kcC9tZHA1L21kcDVfa21zLmgKaW5kZXggNDlkMDExZS4uMWE2YWE0OSAxMDA2NDQKLS0tIGEv ZHJpdmVycy9ncHUvZHJtL21zbS9tZHAvbWRwNS9tZHA1X2ttcy5oCisrKyBiL2RyaXZlcnMvZ3B1 L2RybS9tc20vbWRwL21kcDUvbWRwNV9rbXMuaApAQCAtOTQsNiArOTQsMjQgQEAgc3RydWN0IG1k cDVfcGxhbmVfc3RhdGUgewogI2RlZmluZSB0b19tZHA1X3BsYW5lX3N0YXRlKHgpIFwKIAkJY29u dGFpbmVyX29mKHgsIHN0cnVjdCBtZHA1X3BsYW5lX3N0YXRlLCBiYXNlKQogCitlbnVtIG1kcDVf aW50Zl9tb2RlIHsKKwlNRFA1X0lOVEZfTU9ERV9OT05FID0gMCwKKworCS8qIE1vZGVzIHVzZWQg Zm9yIERTSSBpbnRlcmZhY2UgKElOVEZfRFNJIHR5cGUpOiAqLworCU1EUDVfSU5URl9EU0lfTU9E RV9WSURFTywKKwlNRFA1X0lOVEZfRFNJX01PREVfQ09NTUFORCwKKworCS8qIE1vZGVzIHVzZWQg Zm9yIFdCIGludGVyZmFjZSAoSU5URl9XQiB0eXBlKTogICovCisJTURQNV9JTlRGX1dCX01PREVf QkxPQ0ssCisJTURQNV9JTlRGX1dCX01PREVfTElORSwKK307CisKK3N0cnVjdCBtZHA1X2ludGVy ZmFjZSB7CisJaW50IG51bTsgLyogZGlzcGxheSBpbnRlcmZhY2UgbnVtYmVyICovCisJZW51bSBt ZHA1X2ludGZfdHlwZSB0eXBlOworCWVudW0gbWRwNV9pbnRmX21vZGUgbW9kZTsKK307CisKIHN0 YXRpYyBpbmxpbmUgdm9pZCBtZHA1X3dyaXRlKHN0cnVjdCBtZHA1X2ttcyAqbWRwNV9rbXMsIHUz MiByZWcsIHUzMiBkYXRhKQogewogCW1zbV93cml0ZWwoZGF0YSwgbWRwNV9rbXMtPm1taW8gKyBy ZWcpOwpAQCAtMTMwLDkgKzE0OCw5IEBAIHN0YXRpYyBpbmxpbmUgaW50IHBpcGUybmNsaWVudHMo ZW51bSBtZHA1X3BpcGUgcGlwZSkKIAl9CiB9CiAKLXN0YXRpYyBpbmxpbmUgdWludDMyX3QgaW50 ZjJlcnIoaW50IGludGYpCitzdGF0aWMgaW5saW5lIHVpbnQzMl90IGludGYyZXJyKGludCBpbnRm X251bSkKIHsKLQlzd2l0Y2ggKGludGYpIHsKKwlzd2l0Y2ggKGludGZfbnVtKSB7CiAJY2FzZSAw OiAgcmV0dXJuIE1EUDVfSVJRX0lOVEYwX1VOREVSX1JVTjsKIAljYXNlIDE6ICByZXR1cm4gTURQ NV9JUlFfSU5URjFfVU5ERVJfUlVOOwogCWNhc2UgMjogIHJldHVybiBNRFA1X0lSUV9JTlRGMl9V TkRFUl9SVU47CkBAIC0xNDEsOSArMTU5LDI0IEBAIHN0YXRpYyBpbmxpbmUgdWludDMyX3QgaW50 ZjJlcnIoaW50IGludGYpCiAJfQogfQogCi1zdGF0aWMgaW5saW5lIHVpbnQzMl90IGludGYydmJs YW5rKGludCBpbnRmKQorc3RhdGljIGlubGluZSB1aW50MzJfdCBpbnRmMnZibGFuayhpbnQgbG0s IHN0cnVjdCBtZHA1X2ludGVyZmFjZSAqaW50ZikKIHsKLQlzd2l0Y2ggKGludGYpIHsKKyNkZWZp bmUgR0VUX1BJTkdfUE9OR19JRChsYXllcl9taXhlcikJKChsYXllcl9taXhlciA9PSA1KSA/IDMg OiBsYXllcl9taXhlcikKKworCS8qCisJICogSW4gY2FzZSBvZiBEU0kgQ29tbWFuZCBNb2RlLCB0 aGUgUGluZyBQb25nJ3MgcmVhZCBwb2ludGVyIElSUQorCSAqIGFjdHMgYXMgYSBWYmxhbmsgc2ln bmFsLiBUaGUgUGluZyBQb25nIGJ1ZmZlciB1c2VkIGlzIGJvdW5kIHRvCisJICogbGF5ZXIgbWl4 ZXIuCisJICovCisKKwlpZiAoKGludGYtPnR5cGUgPT0gSU5URl9EU0kpICYmCisJCQkoaW50Zi0+ bW9kZSA9PSBNRFA1X0lOVEZfRFNJX01PREVfQ09NTUFORCkpCisJCXJldHVybiBNRFA1X0lSUV9Q SU5HX1BPTkdfMF9SRF9QVFIgPDwgR0VUX1BJTkdfUE9OR19JRChsbSk7CisKKwlpZiAoaW50Zi0+ dHlwZSA9PSBJTlRGX1dCKQorCQlyZXR1cm4gTURQNV9JUlFfV0JfMl9ET05FOworCisJc3dpdGNo IChpbnRmLT5udW0pIHsKIAljYXNlIDA6ICByZXR1cm4gTURQNV9JUlFfSU5URjBfVlNZTkM7CiAJ Y2FzZSAxOiAgcmV0dXJuIE1EUDVfSVJRX0lOVEYxX1ZTWU5DOwogCWNhc2UgMjogIHJldHVybiBN RFA1X0lSUV9JTlRGMl9WU1lOQzsKQEAgLTE5OCwxMiArMjMxLDExIEBAIHVpbnQzMl90IG1kcDVf Y3J0Y192Ymxhbmsoc3RydWN0IGRybV9jcnRjICpjcnRjKTsKIAogaW50IG1kcDVfY3J0Y19nZXRf bG0oc3RydWN0IGRybV9jcnRjICpjcnRjKTsKIHZvaWQgbWRwNV9jcnRjX2NhbmNlbF9wZW5kaW5n X2ZsaXAoc3RydWN0IGRybV9jcnRjICpjcnRjLCBzdHJ1Y3QgZHJtX2ZpbGUgKmZpbGUpOwotdm9p ZCBtZHA1X2NydGNfc2V0X2ludGYoc3RydWN0IGRybV9jcnRjICpjcnRjLCBpbnQgaW50ZiwKLQkJ ZW51bSBtZHA1X2ludGYgaW50Zl9pZCk7Cit2b2lkIG1kcDVfY3J0Y19zZXRfaW50ZihzdHJ1Y3Qg ZHJtX2NydGMgKmNydGMsIHN0cnVjdCBtZHA1X2ludGVyZmFjZSAqaW50Zik7CiBzdHJ1Y3QgZHJt X2NydGMgKm1kcDVfY3J0Y19pbml0KHN0cnVjdCBkcm1fZGV2aWNlICpkZXYsCiAJCXN0cnVjdCBk cm1fcGxhbmUgKnBsYW5lLCBpbnQgaWQpOwogCi1zdHJ1Y3QgZHJtX2VuY29kZXIgKm1kcDVfZW5j b2Rlcl9pbml0KHN0cnVjdCBkcm1fZGV2aWNlICpkZXYsIGludCBpbnRmLAotCQllbnVtIG1kcDVf aW50ZiBpbnRmX2lkKTsKK3N0cnVjdCBkcm1fZW5jb2RlciAqbWRwNV9lbmNvZGVyX2luaXQoc3Ry dWN0IGRybV9kZXZpY2UgKmRldiwKKwkJc3RydWN0IG1kcDVfaW50ZXJmYWNlICppbnRmKTsKIAog I2VuZGlmIC8qIF9fTURQNV9LTVNfSF9fICovCi0tIApRdWFsY29tbSBJbm5vdmF0aW9uIENlbnRl ciwgSW5jLgoKVGhlIFF1YWxjb21tIElubm92YXRpb24gQ2VudGVyLCBJbmMuIGlzIGEgbWVtYmVy IG9mIHRoZSBDb2RlIEF1cm9yYSBGb3J1bSwgYSBMaW51eCBGb3VuZGF0aW9uIENvbGxhYm9yYXRp dmUgUHJvamVjdAoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X18KZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3Jn Cmh0dHA6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757446AbbCCShr (ORCPT ); Tue, 3 Mar 2015 13:37:47 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:35750 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757193AbbCCSg3 (ORCPT ); Tue, 3 Mar 2015 13:36:29 -0500 From: Stephane Viau To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, robdclark@gmail.com, Stephane Viau Subject: [PATCH 2/4] drm/msm/mdp5: Enhance operation mode for pipeline configuration Date: Tue, 3 Mar 2015 13:36:13 -0500 Message-Id: <1425407775-7704-3-git-send-email-sviau@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1425407775-7704-1-git-send-email-sviau@codeaurora.org> References: <1425407775-7704-1-git-send-email-sviau@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org DSI and WB interfaces need a more complex pipeline configuration than the current mdp5_ctl_set_intf(). For example, memory output connections need to be selected for WB. Interface mode (Video vs. Command modes) also need to be configured for DSI. This change takes care of configuring the whole pipeline as far as operation mode goes. DSI and WB interfaces will be added later. Signed-off-by: Stephane Viau --- drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 2 + drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 39 ++----------- drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 91 +++++++++++++++++++++++++---- drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h | 3 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 29 +++++---- drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 16 ++++- drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 48 ++++++++++++--- 7 files changed, 157 insertions(+), 71 deletions(-) diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h index dba4d52..be587b8 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h @@ -31,6 +31,8 @@ extern const struct mdp5_cfg_hw *mdp5_cfg; typedef DECLARE_BITMAP(mdp5_smp_state_t, MAX_SMP_BLOCKS); +#define MDP5_INTF_IS_VIRTUAL_DISPLAY(intf_type) ((intf_type) >= INTF_VIRTUAL) + #define MDP5_SUB_BLOCK_DEFINITION \ int count; \ uint32_t base[MAX_BASES] diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c index bfba236..15136f1 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c @@ -611,48 +611,17 @@ void mdp5_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file) } /* set interface for routing crtc->encoder: */ -void mdp5_crtc_set_intf(struct drm_crtc *crtc, int intf, - enum mdp5_intf intf_id) +void mdp5_crtc_set_intf(struct drm_crtc *crtc, struct mdp5_interface *intf) { struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); struct mdp5_kms *mdp5_kms = get_kms(crtc); - uint32_t intf_sel; - unsigned long flags; + int lm = mdp5_crtc_get_lm(crtc); /* now that we know what irq's we want: */ - mdp5_crtc->err.irqmask = intf2err(intf); - mdp5_crtc->vblank.irqmask = intf2vblank(intf); + mdp5_crtc->err.irqmask = intf2err(intf->num); + mdp5_crtc->vblank.irqmask = intf2vblank(lm, intf); mdp_irq_update(&mdp5_kms->base); - spin_lock_irqsave(&mdp5_kms->resource_lock, flags); - intf_sel = mdp5_read(mdp5_kms, REG_MDP5_DISP_INTF_SEL); - - switch (intf) { - case 0: - intf_sel &= ~MDP5_DISP_INTF_SEL_INTF0__MASK; - intf_sel |= MDP5_DISP_INTF_SEL_INTF0(intf_id); - break; - case 1: - intf_sel &= ~MDP5_DISP_INTF_SEL_INTF1__MASK; - intf_sel |= MDP5_DISP_INTF_SEL_INTF1(intf_id); - break; - case 2: - intf_sel &= ~MDP5_DISP_INTF_SEL_INTF2__MASK; - intf_sel |= MDP5_DISP_INTF_SEL_INTF2(intf_id); - break; - case 3: - intf_sel &= ~MDP5_DISP_INTF_SEL_INTF3__MASK; - intf_sel |= MDP5_DISP_INTF_SEL_INTF3(intf_id); - break; - default: - BUG(); - break; - } - - mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, intf_sel); - spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); - - DBG("%s: intf_sel=%08x", mdp5_crtc->name, intf_sel); mdp5_ctl_set_intf(mdp5_crtc->ctl, intf); } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c index 1511290..3e88bb7 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c @@ -33,6 +33,16 @@ * requested by the client (in mdp5_crtc_mode_set()). */ +struct op_mode { + struct mdp5_interface intf; + /* + * TODO: add a state variable to control the pipeline + * + * eg: WB interface needs both buffer addresses to be committed + + * output buffers ready to be written into, before we can START. + */ +}; + struct mdp5_ctl { struct mdp5_ctl_manager *ctlm; @@ -41,8 +51,8 @@ struct mdp5_ctl { /* whether this CTL has been allocated or not: */ bool busy; - /* memory output connection (@see mdp5_ctl_mode): */ - u32 mode; + /* Operation Mode Configuration for the Pipeline */ + struct op_mode pipeline; /* REG_MDP5_CTL_*() registers access info + lock: */ spinlock_t hw_lock; @@ -94,19 +104,81 @@ u32 ctl_read(struct mdp5_ctl *ctl, u32 reg) return mdp5_read(mdp5_kms, reg); } +static void set_display_intf(struct mdp5_kms *mdp5_kms, + struct mdp5_interface *intf) +{ + unsigned long flags; + u32 intf_sel; + + spin_lock_irqsave(&mdp5_kms->resource_lock, flags); + intf_sel = mdp5_read(mdp5_kms, REG_MDP5_DISP_INTF_SEL); + + switch (intf->num) { + case 0: + intf_sel &= ~MDP5_DISP_INTF_SEL_INTF0__MASK; + intf_sel |= MDP5_DISP_INTF_SEL_INTF0(intf->type); + break; + case 1: + intf_sel &= ~MDP5_DISP_INTF_SEL_INTF1__MASK; + intf_sel |= MDP5_DISP_INTF_SEL_INTF1(intf->type); + break; + case 2: + intf_sel &= ~MDP5_DISP_INTF_SEL_INTF2__MASK; + intf_sel |= MDP5_DISP_INTF_SEL_INTF2(intf->type); + break; + case 3: + intf_sel &= ~MDP5_DISP_INTF_SEL_INTF3__MASK; + intf_sel |= MDP5_DISP_INTF_SEL_INTF3(intf->type); + break; + default: + BUG(); + break; + } + + mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, intf_sel); + spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); +} -int mdp5_ctl_set_intf(struct mdp5_ctl *ctl, int intf) +static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_interface *intf) { unsigned long flags; - static const enum mdp5_intfnum intfnum[] = { - INTF0, INTF1, INTF2, INTF3, - }; + u32 ctl_op = 0; + + if (!MDP5_INTF_IS_VIRTUAL_DISPLAY(intf->type)) + ctl_op |= MDP5_CTL_OP_INTF_NUM(INTF0 + intf->num); + + switch (intf->type) { + case INTF_DSI: + if (intf->mode == MDP5_INTF_DSI_MODE_COMMAND) + ctl_op |= MDP5_CTL_OP_CMD_MODE; + break; + + case INTF_WB: + if (intf->mode == MDP5_INTF_WB_MODE_LINE) + ctl_op |= MDP5_CTL_OP_MODE(MODE_WB_2_LINE); + break; + + default: + break; + } spin_lock_irqsave(&ctl->hw_lock, flags); - ctl_write(ctl, REG_MDP5_CTL_OP(ctl->id), - MDP5_CTL_OP_MODE(ctl->mode) | - MDP5_CTL_OP_INTF_NUM(intfnum[intf])); + ctl_write(ctl, REG_MDP5_CTL_OP(ctl->id), ctl_op); spin_unlock_irqrestore(&ctl->hw_lock, flags); +} + +int mdp5_ctl_set_intf(struct mdp5_ctl *ctl, struct mdp5_interface *intf) +{ + struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm; + struct mdp5_kms *mdp5_kms = get_kms(ctl_mgr); + + memcpy(&ctl->pipeline.intf, intf, sizeof(*intf)); + + /* Virtual interfaces need not set a display intf (e.g.: Writeback) */ + if (!MDP5_INTF_IS_VIRTUAL_DISPLAY(intf->type)) + set_display_intf(mdp5_kms, intf); + + set_ctl_op(ctl, intf); return 0; } @@ -303,7 +375,6 @@ struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev, } ctl->ctlm = ctl_mgr; ctl->id = c; - ctl->mode = MODE_NONE; ctl->reg_offset = ctl_cfg->base[c]; ctl->flush_mask = MDP5_CTL_FLUSH_CTL; ctl->busy = false; diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h index ad48788..271d5ac 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h @@ -34,7 +34,8 @@ void mdp5_ctlm_destroy(struct mdp5_ctl_manager *ctlm); */ struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctlm, struct drm_crtc *crtc); -int mdp5_ctl_set_intf(struct mdp5_ctl *ctl, int intf); +struct mdp5_interface; +int mdp5_ctl_set_intf(struct mdp5_ctl *ctl, struct mdp5_interface *intf); int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, bool enable); diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c index a09fa58..f3b6fe8 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c @@ -23,8 +23,7 @@ struct mdp5_encoder { struct drm_encoder base; - int intf; - enum mdp5_intf intf_id; + struct mdp5_interface intf; spinlock_t intf_lock; /* protect REG_MDP5_INTF_* registers */ bool enabled; uint32_t bsc; @@ -126,7 +125,7 @@ static void mdp5_encoder_mode_set(struct drm_encoder *encoder, struct mdp5_kms *mdp5_kms = get_kms(encoder); struct drm_device *dev = encoder->dev; struct drm_connector *connector; - int intf = mdp5_encoder->intf; + int intf = mdp5_encoder->intf.num; uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol; uint32_t display_v_start, display_v_end; uint32_t hsync_start_x, hsync_end_x; @@ -188,7 +187,7 @@ static void mdp5_encoder_mode_set(struct drm_encoder *encoder, * DISPLAY_V_START = (VBP * HCYCLE) + HBP * DISPLAY_V_END = (VBP + VACTIVE) * HCYCLE - 1 - HFP */ - if (mdp5_encoder->intf_id == INTF_eDP) { + if (mdp5_encoder->intf.type == INTF_eDP) { display_v_start += mode->htotal - mode->hsync_start; display_v_end -= mode->hsync_start - mode->hdisplay; } @@ -224,14 +223,16 @@ static void mdp5_encoder_disable(struct drm_encoder *encoder) { struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); struct mdp5_kms *mdp5_kms = get_kms(encoder); - int intf = mdp5_encoder->intf; + int lm = mdp5_crtc_get_lm(encoder->crtc); + struct mdp5_interface *intf = &mdp5_encoder->intf; + int intfn = mdp5_encoder->intf.num; unsigned long flags; if (WARN_ON(!mdp5_encoder->enabled)) return; spin_lock_irqsave(&mdp5_encoder->intf_lock, flags); - mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intf), 0); + mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 0); spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags); /* @@ -242,7 +243,7 @@ static void mdp5_encoder_disable(struct drm_encoder *encoder) * the settings changes for the new modeset (like new * scanout buffer) don't latch properly.. */ - mdp_irq_wait(&mdp5_kms->base, intf2vblank(intf)); + mdp_irq_wait(&mdp5_kms->base, intf2vblank(lm, intf)); bs_set(mdp5_encoder, 0); @@ -253,18 +254,17 @@ static void mdp5_encoder_enable(struct drm_encoder *encoder) { struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); struct mdp5_kms *mdp5_kms = get_kms(encoder); - int intf = mdp5_encoder->intf; + int intfn = mdp5_encoder->intf.num; unsigned long flags; if (WARN_ON(mdp5_encoder->enabled)) return; - mdp5_crtc_set_intf(encoder->crtc, mdp5_encoder->intf, - mdp5_encoder->intf_id); + mdp5_crtc_set_intf(encoder->crtc, &mdp5_encoder->intf); bs_set(mdp5_encoder, 1); spin_lock_irqsave(&mdp5_encoder->intf_lock, flags); - mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intf), 1); + mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 1); spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags); mdp5_encoder->enabled = true; @@ -278,8 +278,8 @@ static const struct drm_encoder_helper_funcs mdp5_encoder_helper_funcs = { }; /* initialize encoder */ -struct drm_encoder *mdp5_encoder_init(struct drm_device *dev, int intf, - enum mdp5_intf intf_id) +struct drm_encoder *mdp5_encoder_init(struct drm_device *dev, + struct mdp5_interface *intf) { struct drm_encoder *encoder = NULL; struct mdp5_encoder *mdp5_encoder; @@ -291,8 +291,7 @@ struct drm_encoder *mdp5_encoder_init(struct drm_device *dev, int intf, goto fail; } - mdp5_encoder->intf = intf; - mdp5_encoder->intf_id = intf_id; + memcpy(&mdp5_encoder->intf, intf, sizeof(mdp5_encoder->intf)); encoder = &mdp5_encoder->base; spin_lock_init(&mdp5_encoder->intf_lock); diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c index 92b61db..390d9d2 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c @@ -223,8 +223,14 @@ static int modeset_init(struct mdp5_kms *mdp5_kms) } if (priv->hdmi) { + struct mdp5_interface intf = { + .num = 3, + .type = INTF_HDMI, + .mode = MDP5_INTF_MODE_NONE, + }; + /* Construct encoder for HDMI: */ - encoder = mdp5_encoder_init(dev, 3, INTF_HDMI); + encoder = mdp5_encoder_init(dev, &intf); if (IS_ERR(encoder)) { dev_err(dev->dev, "failed to construct encoder\n"); ret = PTR_ERR(encoder); @@ -242,8 +248,14 @@ static int modeset_init(struct mdp5_kms *mdp5_kms) } if (priv->edp) { + struct mdp5_interface intf = { + .num = 0, + .type = INTF_eDP, + .mode = MDP5_INTF_MODE_NONE, + }; + /* Construct encoder for eDP: */ - encoder = mdp5_encoder_init(dev, 0, INTF_eDP); + encoder = mdp5_encoder_init(dev, &intf); if (IS_ERR(encoder)) { dev_err(dev->dev, "failed to construct eDP encoder\n"); ret = PTR_ERR(encoder); diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h index 49d011e..1a6aa49 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h @@ -94,6 +94,24 @@ struct mdp5_plane_state { #define to_mdp5_plane_state(x) \ container_of(x, struct mdp5_plane_state, base) +enum mdp5_intf_mode { + MDP5_INTF_MODE_NONE = 0, + + /* Modes used for DSI interface (INTF_DSI type): */ + MDP5_INTF_DSI_MODE_VIDEO, + MDP5_INTF_DSI_MODE_COMMAND, + + /* Modes used for WB interface (INTF_WB type): */ + MDP5_INTF_WB_MODE_BLOCK, + MDP5_INTF_WB_MODE_LINE, +}; + +struct mdp5_interface { + int num; /* display interface number */ + enum mdp5_intf_type type; + enum mdp5_intf_mode mode; +}; + static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data) { msm_writel(data, mdp5_kms->mmio + reg); @@ -130,9 +148,9 @@ static inline int pipe2nclients(enum mdp5_pipe pipe) } } -static inline uint32_t intf2err(int intf) +static inline uint32_t intf2err(int intf_num) { - switch (intf) { + switch (intf_num) { case 0: return MDP5_IRQ_INTF0_UNDER_RUN; case 1: return MDP5_IRQ_INTF1_UNDER_RUN; case 2: return MDP5_IRQ_INTF2_UNDER_RUN; @@ -141,9 +159,24 @@ static inline uint32_t intf2err(int intf) } } -static inline uint32_t intf2vblank(int intf) +static inline uint32_t intf2vblank(int lm, struct mdp5_interface *intf) { - switch (intf) { +#define GET_PING_PONG_ID(layer_mixer) ((layer_mixer == 5) ? 3 : layer_mixer) + + /* + * In case of DSI Command Mode, the Ping Pong's read pointer IRQ + * acts as a Vblank signal. The Ping Pong buffer used is bound to + * layer mixer. + */ + + if ((intf->type == INTF_DSI) && + (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) + return MDP5_IRQ_PING_PONG_0_RD_PTR << GET_PING_PONG_ID(lm); + + if (intf->type == INTF_WB) + return MDP5_IRQ_WB_2_DONE; + + switch (intf->num) { case 0: return MDP5_IRQ_INTF0_VSYNC; case 1: return MDP5_IRQ_INTF1_VSYNC; case 2: return MDP5_IRQ_INTF2_VSYNC; @@ -198,12 +231,11 @@ uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc); int mdp5_crtc_get_lm(struct drm_crtc *crtc); void mdp5_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file); -void mdp5_crtc_set_intf(struct drm_crtc *crtc, int intf, - enum mdp5_intf intf_id); +void mdp5_crtc_set_intf(struct drm_crtc *crtc, struct mdp5_interface *intf); struct drm_crtc *mdp5_crtc_init(struct drm_device *dev, struct drm_plane *plane, int id); -struct drm_encoder *mdp5_encoder_init(struct drm_device *dev, int intf, - enum mdp5_intf intf_id); +struct drm_encoder *mdp5_encoder_init(struct drm_device *dev, + struct mdp5_interface *intf); #endif /* __MDP5_KMS_H__ */ -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project