Re: [PATCH v3 0/2] Add support for Xilinx ZynqMP SoC

[Ian Campbell <ian.campbell@citrix.com>]

On Wed, 2015-03-11 at 09:59 +1000, Edgar E. Iglesias wrote:
> On Tue, Mar 10, 2015 at 11:30:10AM +0000, Julien Grall wrote:
> > Hello Edgar,
> > 
> > Thank you for adding support of the ZynqMP.
> > 
> > On 10/03/15 02:49, Edgar E. Iglesias wrote:
> > > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> > > 
> > > Adds support for the Cadence UART in Xilinx ZynqMP. The
> > > rest of the ZynqMP platform is discovered via device-tree.
> > 
> > Did you make sure that the default grant table range (0xb0000000 -
> > 0xb0020000) don't overlap with an hardware region?
> 
> No I didn't, thanks for pointing that out. I need to move these to
> another address.
> 
> So now I'm back to needing platform specific code. Long term,
> Maybe it would make sense making the grant table range somehow
> configurable via DT?

The plan is to have Xen preallocate the grant table pages and expose
their physical address to dom0, so when dom0 then maps it 1:1 it won't
clash with either memory used by Xen or by the dom0's actual assigned
memory and since it is RAM it can't possibly clash with any MMIO.

> Anyway, I'll send a v4 with the platform code to move the gnt
> into a reserved area in the memory map.

Ian.