From mboxrd@z Thu Jan 1 00:00:00 1970 From: Hai Li Subject: [PATCH 1/4] drm/msm/dsi: Update generated DSI header file Date: Fri, 13 Mar 2015 19:24:15 -0400 Message-ID: <1426289058-6663-2-git-send-email-hali@codeaurora.org> References: <1426289058-6663-1-git-send-email-hali@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1426289058-6663-1-git-send-email-hali@codeaurora.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org UHJlcGFyZSBmb3IgaW5pdGlhbCBEU0kgaW1wbGVtZW50YXRpb24KClNpZ25lZC1vZmYtYnk6IEhh aSBMaSA8aGFsaUBjb2RlYXVyb3JhLm9yZz4KLS0tCiBkcml2ZXJzL2dwdS9kcm0vbXNtL2RzaS9k c2kueG1sLmggfCA0MTggKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKy0tLS0KIDEg ZmlsZSBjaGFuZ2VkLCAzNzYgaW5zZXJ0aW9ucygrKSwgNDIgZGVsZXRpb25zKC0pCgpkaWZmIC0t Z2l0IGEvZHJpdmVycy9ncHUvZHJtL21zbS9kc2kvZHNpLnhtbC5oIGIvZHJpdmVycy9ncHUvZHJt L21zbS9kc2kvZHNpLnhtbC5oCmluZGV4IGFiZjFiYmEuLjFkY2ZhZTIgMTAwNjQ0Ci0tLSBhL2Ry aXZlcnMvZ3B1L2RybS9tc20vZHNpL2RzaS54bWwuaAorKysgYi9kcml2ZXJzL2dwdS9kcm0vbXNt L2RzaS9kc2kueG1sLmgKQEAgLTgsMTkgKzgsMTAgQEAgaHR0cDovL2dpdGh1Yi5jb20vZnJlZWRy ZW5vL2Vudnl0b29scy8KIGdpdCBjbG9uZSBodHRwczovL2dpdGh1Yi5jb20vZnJlZWRyZW5vL2Vu dnl0b29scy5naXQKIAogVGhlIHJ1bGVzLW5nLW5nIHNvdXJjZSBmaWxlcyB0aGlzIGhlYWRlciB3 YXMgZ2VuZXJhdGVkIGZyb20gYXJlOgotLSAvaG9tZS9yb2JjbGFyay9zcmMvZnJlZWRyZW5vL2Vu dnl0b29scy9ybm5kYi9tc20ueG1sICAgICAgICAgICAgICAgICAoICAgIDY3NiBieXRlcywgZnJv bSAyMDE0LTEyLTA1IDE1OjM0OjQ5KQotLSAvaG9tZS9yb2JjbGFyay9zcmMvZnJlZWRyZW5vL2Vu dnl0b29scy9ybm5kYi9mcmVlZHJlbm9fY29weXJpZ2h0LnhtbCAoICAgMTQ1MyBieXRlcywgZnJv bSAyMDEzLTAzLTMxIDE2OjUxOjI3KQotLSAvaG9tZS9yb2JjbGFyay9zcmMvZnJlZWRyZW5vL2Vu dnl0b29scy9ybm5kYi9tZHAvbWRwNC54bWwgICAgICAgICAgICAoICAyMDkwOCBieXRlcywgZnJv bSAyMDE0LTEyLTA4IDE2OjEzOjAwKQotLSAvaG9tZS9yb2JjbGFyay9zcmMvZnJlZWRyZW5vL2Vu dnl0b29scy9ybm5kYi9tZHAvbWRwX2NvbW1vbi54bWwgICAgICAoICAgMjM1NyBieXRlcywgZnJv bSAyMDE0LTEyLTA4IDE2OjEzOjAwKQotLSAvaG9tZS9yb2JjbGFyay9zcmMvZnJlZWRyZW5vL2Vu dnl0b29scy9ybm5kYi9tZHAvbWRwNS54bWwgICAgICAgICAgICAoICAyNzIwOCBieXRlcywgZnJv bSAyMDE1LTAxLTEzIDIzOjU2OjExKQotLSAvaG9tZS9yb2JjbGFyay9zcmMvZnJlZWRyZW5vL2Vu dnl0b29scy9ybm5kYi9kc2kvZHNpLnhtbCAgICAgICAgICAgICAoICAxMTcxMiBieXRlcywgZnJv bSAyMDEzLTA4LTE3IDE3OjEzOjQzKQotLSAvaG9tZS9yb2JjbGFyay9zcmMvZnJlZWRyZW5vL2Vu dnl0b29scy9ybm5kYi9kc2kvc2ZwYi54bWwgICAgICAgICAgICAoICAgIDM0NCBieXRlcywgZnJv bSAyMDEzLTA4LTExIDE5OjI2OjMyKQotLSAvaG9tZS9yb2JjbGFyay9zcmMvZnJlZWRyZW5vL2Vu dnl0b29scy9ybm5kYi9kc2kvbW1zc19jYy54bWwgICAgICAgICAoICAgMTY4NiBieXRlcywgZnJv bSAyMDE0LTEwLTMxIDE2OjQ4OjU3KQotLSAvaG9tZS9yb2JjbGFyay9zcmMvZnJlZWRyZW5vL2Vu dnl0b29scy9ybm5kYi9oZG1pL3FmcHJvbS54bWwgICAgICAgICAoICAgIDYwMCBieXRlcywgZnJv bSAyMDEzLTA3LTA1IDE5OjIxOjEyKQotLSAvaG9tZS9yb2JjbGFyay9zcmMvZnJlZWRyZW5vL2Vu dnl0b29scy9ybm5kYi9oZG1pL2hkbWkueG1sICAgICAgICAgICAoICAyNjg0OCBieXRlcywgZnJv bSAyMDE1LTAxLTEzIDIzOjU1OjU3KQotLSAvaG9tZS9yb2JjbGFyay9zcmMvZnJlZWRyZW5vL2Vu dnl0b29scy9ybm5kYi9lZHAvZWRwLnhtbCAgICAgICAgICAgICAoICAgODI1MyBieXRlcywgZnJv bSAyMDE0LTEyLTA4IDE2OjEzOjAwKQotCi1Db3B5cmlnaHQgKEMpIDIwMTMgYnkgdGhlIGZvbGxv d2luZyBhdXRob3JzOgorLSAvdXNyMi9oYWxpL2xvY2FsL2Vudnl0b29scy9lbnZ5dG9vbHMvcm5u ZGIvZHNpL2RzaS54bWwgICAgICAgICAgICAgKCAgMTg2ODEgYnl0ZXMsIGZyb20gMjAxNS0wMy0w NCAyMzowODozMSkKKy0gL3VzcjIvaGFsaS9sb2NhbC9lbnZ5dG9vbHMvZW52eXRvb2xzL3JubmRi L2ZyZWVkcmVub19jb3B5cmlnaHQueG1sICggICAxNDUzIGJ5dGVzLCBmcm9tIDIwMTUtMDEtMjgg MjE6NDM6MjIpCisKK0NvcHlyaWdodCAoQykgMjAxMy0yMDE1IGJ5IHRoZSBmb2xsb3dpbmcgYXV0 aG9yczoKIC0gUm9iIENsYXJrIDxyb2JkY2xhcmtAZ21haWwuY29tPiAocm9iY2xhcmspCiAKIFBl cm1pc3Npb24gaXMgaGVyZWJ5IGdyYW50ZWQsIGZyZWUgb2YgY2hhcmdlLCB0byBhbnkgcGVyc29u IG9idGFpbmluZwpAQCAtNTEsMTEgKzQyLDExIEBAIGVudW0gZHNpX3RyYWZmaWNfbW9kZSB7CiAJ QlVSU1RfTU9ERSA9IDIsCiB9OwogCi1lbnVtIGRzaV9kc3RfZm9ybWF0IHsKLQlEU1RfRk9STUFU X1JHQjU2NSA9IDAsCi0JRFNUX0ZPUk1BVF9SR0I2NjYgPSAxLAotCURTVF9GT1JNQVRfUkdCNjY2 X0xPT1NFID0gMiwKLQlEU1RfRk9STUFUX1JHQjg4OCA9IDMsCitlbnVtIGRzaV92aWRfZHN0X2Zv cm1hdCB7CisJVklEX0RTVF9GT1JNQVRfUkdCNTY1ID0gMCwKKwlWSURfRFNUX0ZPUk1BVF9SR0I2 NjYgPSAxLAorCVZJRF9EU1RfRk9STUFUX1JHQjY2Nl9MT09TRSA9IDIsCisJVklEX0RTVF9GT1JN QVRfUkdCODg4ID0gMywKIH07CiAKIGVudW0gZHNpX3JnYl9zd2FwIHsKQEAgLTY5LDIwICs2MCw2 MyBAQCBlbnVtIGRzaV9yZ2Jfc3dhcCB7CiAKIGVudW0gZHNpX2NtZF90cmlnZ2VyIHsKIAlUUklH R0VSX05PTkUgPSAwLAorCVRSSUdHRVJfU0VPRiA9IDEsCiAJVFJJR0dFUl9URSA9IDIsCiAJVFJJ R0dFUl9TVyA9IDQsCiAJVFJJR0dFUl9TV19TRU9GID0gNSwKIAlUUklHR0VSX1NXX1RFID0gNiwK IH07CiAKK2VudW0gZHNpX2NtZF9kc3RfZm9ybWF0IHsKKwlDTURfRFNUX0ZPUk1BVF9SR0IxMTEg PSAwLAorCUNNRF9EU1RfRk9STUFUX1JHQjMzMiA9IDMsCisJQ01EX0RTVF9GT1JNQVRfUkdCNDQ0 ID0gNCwKKwlDTURfRFNUX0ZPUk1BVF9SR0I1NjUgPSA2LAorCUNNRF9EU1RfRk9STUFUX1JHQjY2 NiA9IDcsCisJQ01EX0RTVF9GT1JNQVRfUkdCODg4ID0gOCwKK307CisKK2VudW0gZHNpX2xhbmVf c3dhcCB7CisJTEFORV9TV0FQXzAxMjMgPSAwLAorCUxBTkVfU1dBUF8zMDEyID0gMSwKKwlMQU5F X1NXQVBfMjMwMSA9IDIsCisJTEFORV9TV0FQXzEyMzAgPSAzLAorCUxBTkVfU1dBUF8wMzIxID0g NCwKKwlMQU5FX1NXQVBfMTAzMiA9IDUsCisJTEFORV9TV0FQXzIxMDMgPSA2LAorCUxBTkVfU1dB UF8zMjEwID0gNywKK307CisKICNkZWZpbmUgRFNJX0lSUV9DTURfRE1BX0RPTkUJCQkJCTB4MDAw MDAwMDEKICNkZWZpbmUgRFNJX0lSUV9NQVNLX0NNRF9ETUFfRE9ORQkJCQkweDAwMDAwMDAyCiAj ZGVmaW5lIERTSV9JUlFfQ01EX01EUF9ET05FCQkJCQkweDAwMDAwMTAwCiAjZGVmaW5lIERTSV9J UlFfTUFTS19DTURfTURQX0RPTkUJCQkJMHgwMDAwMDIwMAogI2RlZmluZSBEU0lfSVJRX1ZJREVP X0RPTkUJCQkJCTB4MDAwMTAwMDAKICNkZWZpbmUgRFNJX0lSUV9NQVNLX1ZJREVPX0RPTkUJCQkJ CTB4MDAwMjAwMDAKKyNkZWZpbmUgRFNJX0lSUV9CVEFfRE9ORQkJCQkJMHgwMDEwMDAwMAorI2Rl ZmluZSBEU0lfSVJRX01BU0tfQlRBX0RPTkUJCQkJCTB4MDAyMDAwMDAKICNkZWZpbmUgRFNJX0lS UV9FUlJPUgkJCQkJCTB4MDEwMDAwMDAKICNkZWZpbmUgRFNJX0lSUV9NQVNLX0VSUk9SCQkJCQkw eDAyMDAwMDAwCisjZGVmaW5lIFJFR19EU0lfNkdfSFdfVkVSU0lPTgkJCQkJMHgwMDAwMDAwMAor I2RlZmluZSBEU0lfNkdfSFdfVkVSU0lPTl9NQUpPUl9fTUFTSwkJCQkweGYwMDAwMDAwCisjZGVm aW5lIERTSV82R19IV19WRVJTSU9OX01BSk9SX19TSElGVAkJCQkyOAorc3RhdGljIGlubGluZSB1 aW50MzJfdCBEU0lfNkdfSFdfVkVSU0lPTl9NQUpPUih1aW50MzJfdCB2YWwpCit7CisJcmV0dXJu ICgodmFsKSA8PCBEU0lfNkdfSFdfVkVSU0lPTl9NQUpPUl9fU0hJRlQpICYgRFNJXzZHX0hXX1ZF UlNJT05fTUFKT1JfX01BU0s7Cit9CisjZGVmaW5lIERTSV82R19IV19WRVJTSU9OX01JTk9SX19N QVNLCQkJCTB4MGZmZjAwMDAKKyNkZWZpbmUgRFNJXzZHX0hXX1ZFUlNJT05fTUlOT1JfX1NISUZU CQkJCTE2CitzdGF0aWMgaW5saW5lIHVpbnQzMl90IERTSV82R19IV19WRVJTSU9OX01JTk9SKHVp bnQzMl90IHZhbCkKK3sKKwlyZXR1cm4gKCh2YWwpIDw8IERTSV82R19IV19WRVJTSU9OX01JTk9S X19TSElGVCkgJiBEU0lfNkdfSFdfVkVSU0lPTl9NSU5PUl9fTUFTSzsKK30KKyNkZWZpbmUgRFNJ XzZHX0hXX1ZFUlNJT05fU1RFUF9fTUFTSwkJCQkweDAwMDBmZmZmCisjZGVmaW5lIERTSV82R19I V19WRVJTSU9OX1NURVBfX1NISUZUCQkJCTAKK3N0YXRpYyBpbmxpbmUgdWludDMyX3QgRFNJXzZH X0hXX1ZFUlNJT05fU1RFUCh1aW50MzJfdCB2YWwpCit7CisJcmV0dXJuICgodmFsKSA8PCBEU0lf NkdfSFdfVkVSU0lPTl9TVEVQX19TSElGVCkgJiBEU0lfNkdfSFdfVkVSU0lPTl9TVEVQX19NQVNL OworfQorCiAjZGVmaW5lIFJFR19EU0lfQ1RSTAkJCQkJCTB4MDAwMDAwMDAKICNkZWZpbmUgRFNJ X0NUUkxfRU5BQkxFCQkJCQkJMHgwMDAwMDAwMQogI2RlZmluZSBEU0lfQ1RSTF9WSURfTU9ERV9F TgkJCQkJMHgwMDAwMDAwMgpAQCAtOTYsMTEgKzEzMCwxNSBAQCBlbnVtIGRzaV9jbWRfdHJpZ2dl ciB7CiAjZGVmaW5lIERTSV9DVFJMX0NSQ19DSEVDSwkJCQkJMHgwMTAwMDAwMAogCiAjZGVmaW5l IFJFR19EU0lfU1RBVFVTMAkJCQkJCTB4MDAwMDAwMDQKKyNkZWZpbmUgRFNJX1NUQVRVUzBfQ01E X01PREVfRU5HSU5FX0JVU1kJCQkweDAwMDAwMDAxCiAjZGVmaW5lIERTSV9TVEFUVVMwX0NNRF9N T0RFX0RNQV9CVVNZCQkJCTB4MDAwMDAwMDIKKyNkZWZpbmUgRFNJX1NUQVRVUzBfQ01EX01PREVf TURQX0JVU1kJCQkJMHgwMDAwMDAwNAogI2RlZmluZSBEU0lfU1RBVFVTMF9WSURFT19NT0RFX0VO R0lORV9CVVNZCQkJMHgwMDAwMDAwOAogI2RlZmluZSBEU0lfU1RBVFVTMF9EU0lfQlVTWQkJCQkJ MHgwMDAwMDAxMAorI2RlZmluZSBEU0lfU1RBVFVTMF9JTlRFUkxFQVZFX09QX0NPTlRFTlRJT04J CQkweDgwMDAwMDAwCiAKICNkZWZpbmUgUkVHX0RTSV9GSUZPX1NUQVRVUwkJCQkJMHgwMDAwMDAw OAorI2RlZmluZSBEU0lfRklGT19TVEFUVVNfQ01EX01EUF9GSUZPX1VOREVSRkxPVwkJCTB4MDAw MDAwODAKIAogI2RlZmluZSBSRUdfRFNJX1ZJRF9DRkcwCQkJCQkweDAwMDAwMDBjCiAjZGVmaW5l IERTSV9WSURfQ0ZHMF9WSVJUX0NIQU5ORUxfX01BU0sJCQkJMHgwMDAwMDAwMwpAQCAtMTExLDcg KzE0OSw3IEBAIHN0YXRpYyBpbmxpbmUgdWludDMyX3QgRFNJX1ZJRF9DRkcwX1ZJUlRfQ0hBTk5F TCh1aW50MzJfdCB2YWwpCiB9CiAjZGVmaW5lIERTSV9WSURfQ0ZHMF9EU1RfRk9STUFUX19NQVNL CQkJCTB4MDAwMDAwMzAKICNkZWZpbmUgRFNJX1ZJRF9DRkcwX0RTVF9GT1JNQVRfX1NISUZUCQkJ CTQKLXN0YXRpYyBpbmxpbmUgdWludDMyX3QgRFNJX1ZJRF9DRkcwX0RTVF9GT1JNQVQoZW51bSBk c2lfZHN0X2Zvcm1hdCB2YWwpCitzdGF0aWMgaW5saW5lIHVpbnQzMl90IERTSV9WSURfQ0ZHMF9E U1RfRk9STUFUKGVudW0gZHNpX3ZpZF9kc3RfZm9ybWF0IHZhbCkKIHsKIAlyZXR1cm4gKCh2YWwp IDw8IERTSV9WSURfQ0ZHMF9EU1RfRk9STUFUX19TSElGVCkgJiBEU0lfVklEX0NGRzBfRFNUX0ZP Uk1BVF9fTUFTSzsKIH0KQEAgLTEyOSwyMSArMTY3LDE1IEBAIHN0YXRpYyBpbmxpbmUgdWludDMy X3QgRFNJX1ZJRF9DRkcwX1RSQUZGSUNfTU9ERShlbnVtIGRzaV90cmFmZmljX21vZGUgdmFsKQog I2RlZmluZSBEU0lfVklEX0NGRzBfUFVMU0VfTU9ERV9IU0FfSEUJCQkJMHgxMDAwMDAwMAogCiAj ZGVmaW5lIFJFR19EU0lfVklEX0NGRzEJCQkJCTB4MDAwMDAwMWMKLSNkZWZpbmUgRFNJX1ZJRF9D RkcxX1JfU0VMCQkJCQkweDAwMDAwMDEwCi0jZGVmaW5lIERTSV9WSURfQ0ZHMV9HX1NFTAkJCQkJ MHgwMDAwMDEwMAotI2RlZmluZSBEU0lfVklEX0NGRzFfQl9TRUwJCQkJCTB4MDAwMDEwMDAKLSNk ZWZpbmUgRFNJX1ZJRF9DRkcxX1JHQl9TV0FQX19NQVNLCQkJCTB4MDAwNzAwMDAKLSNkZWZpbmUg RFNJX1ZJRF9DRkcxX1JHQl9TV0FQX19TSElGVAkJCQkxNgorI2RlZmluZSBEU0lfVklEX0NGRzFf Ul9TRUwJCQkJCTB4MDAwMDAwMDEKKyNkZWZpbmUgRFNJX1ZJRF9DRkcxX0dfU0VMCQkJCQkweDAw MDAwMDEwCisjZGVmaW5lIERTSV9WSURfQ0ZHMV9CX1NFTAkJCQkJMHgwMDAwMDEwMAorI2RlZmlu ZSBEU0lfVklEX0NGRzFfUkdCX1NXQVBfX01BU0sJCQkJMHgwMDAwNzAwMAorI2RlZmluZSBEU0lf VklEX0NGRzFfUkdCX1NXQVBfX1NISUZUCQkJCTEyCiBzdGF0aWMgaW5saW5lIHVpbnQzMl90IERT SV9WSURfQ0ZHMV9SR0JfU1dBUChlbnVtIGRzaV9yZ2Jfc3dhcCB2YWwpCiB7CiAJcmV0dXJuICgo dmFsKSA8PCBEU0lfVklEX0NGRzFfUkdCX1NXQVBfX1NISUZUKSAmIERTSV9WSURfQ0ZHMV9SR0Jf U1dBUF9fTUFTSzsKIH0KLSNkZWZpbmUgRFNJX1ZJRF9DRkcxX0lOVEVSTEVBVkVfTUFYX19NQVNL CQkJMHgwMGYwMDAwMAotI2RlZmluZSBEU0lfVklEX0NGRzFfSU5URVJMRUFWRV9NQVhfX1NISUZU CQkJMjAKLXN0YXRpYyBpbmxpbmUgdWludDMyX3QgRFNJX1ZJRF9DRkcxX0lOVEVSTEVBVkVfTUFY KHVpbnQzMl90IHZhbCkKLXsKLQlyZXR1cm4gKCh2YWwpIDw8IERTSV9WSURfQ0ZHMV9JTlRFUkxF QVZFX01BWF9fU0hJRlQpICYgRFNJX1ZJRF9DRkcxX0lOVEVSTEVBVkVfTUFYX19NQVNLOwotfQog CiAjZGVmaW5lIFJFR19EU0lfQUNUSVZFX0gJCQkJCTB4MDAwMDAwMjAKICNkZWZpbmUgRFNJX0FD VElWRV9IX1NUQVJUX19NQVNLCQkJCTB4MDAwMDBmZmYKQEAgLTIwMSwzMiArMjMzLDExNSBAQCBz dGF0aWMgaW5saW5lIHVpbnQzMl90IERTSV9BQ1RJVkVfSFNZTkNfRU5EKHVpbnQzMl90IHZhbCkK IAlyZXR1cm4gKCh2YWwpIDw8IERTSV9BQ1RJVkVfSFNZTkNfRU5EX19TSElGVCkgJiBEU0lfQUNU SVZFX0hTWU5DX0VORF9fTUFTSzsKIH0KIAotI2RlZmluZSBSRUdfRFNJX0FDVElWRV9WU1lOQwkJ CQkJMHgwMDAwMDAzNAotI2RlZmluZSBEU0lfQUNUSVZFX1ZTWU5DX1NUQVJUX19NQVNLCQkJCTB4 MDAwMDBmZmYKLSNkZWZpbmUgRFNJX0FDVElWRV9WU1lOQ19TVEFSVF9fU0hJRlQJCQkJMAotc3Rh dGljIGlubGluZSB1aW50MzJfdCBEU0lfQUNUSVZFX1ZTWU5DX1NUQVJUKHVpbnQzMl90IHZhbCkK KyNkZWZpbmUgUkVHX0RTSV9BQ1RJVkVfVlNZTkNfSFBPUwkJCQkweDAwMDAwMDMwCisjZGVmaW5l IERTSV9BQ1RJVkVfVlNZTkNfSFBPU19TVEFSVF9fTUFTSwkJCTB4MDAwMDBmZmYKKyNkZWZpbmUg RFNJX0FDVElWRV9WU1lOQ19IUE9TX1NUQVJUX19TSElGVAkJCTAKK3N0YXRpYyBpbmxpbmUgdWlu dDMyX3QgRFNJX0FDVElWRV9WU1lOQ19IUE9TX1NUQVJUKHVpbnQzMl90IHZhbCkKIHsKLQlyZXR1 cm4gKCh2YWwpIDw8IERTSV9BQ1RJVkVfVlNZTkNfU1RBUlRfX1NISUZUKSAmIERTSV9BQ1RJVkVf VlNZTkNfU1RBUlRfX01BU0s7CisJcmV0dXJuICgodmFsKSA8PCBEU0lfQUNUSVZFX1ZTWU5DX0hQ T1NfU1RBUlRfX1NISUZUKSAmIERTSV9BQ1RJVkVfVlNZTkNfSFBPU19TVEFSVF9fTUFTSzsKIH0K LSNkZWZpbmUgRFNJX0FDVElWRV9WU1lOQ19FTkRfX01BU0sJCQkJMHgwZmZmMDAwMAotI2RlZmlu ZSBEU0lfQUNUSVZFX1ZTWU5DX0VORF9fU0hJRlQJCQkJMTYKLXN0YXRpYyBpbmxpbmUgdWludDMy X3QgRFNJX0FDVElWRV9WU1lOQ19FTkQodWludDMyX3QgdmFsKQorI2RlZmluZSBEU0lfQUNUSVZF X1ZTWU5DX0hQT1NfRU5EX19NQVNLCQkJCTB4MGZmZjAwMDAKKyNkZWZpbmUgRFNJX0FDVElWRV9W U1lOQ19IUE9TX0VORF9fU0hJRlQJCQkxNgorc3RhdGljIGlubGluZSB1aW50MzJfdCBEU0lfQUNU SVZFX1ZTWU5DX0hQT1NfRU5EKHVpbnQzMl90IHZhbCkKIHsKLQlyZXR1cm4gKCh2YWwpIDw8IERT SV9BQ1RJVkVfVlNZTkNfRU5EX19TSElGVCkgJiBEU0lfQUNUSVZFX1ZTWU5DX0VORF9fTUFTSzsK KwlyZXR1cm4gKCh2YWwpIDw8IERTSV9BQ1RJVkVfVlNZTkNfSFBPU19FTkRfX1NISUZUKSAmIERT SV9BQ1RJVkVfVlNZTkNfSFBPU19FTkRfX01BU0s7Cit9CisKKyNkZWZpbmUgUkVHX0RTSV9BQ1RJ VkVfVlNZTkNfVlBPUwkJCQkweDAwMDAwMDM0CisjZGVmaW5lIERTSV9BQ1RJVkVfVlNZTkNfVlBP U19TVEFSVF9fTUFTSwkJCTB4MDAwMDBmZmYKKyNkZWZpbmUgRFNJX0FDVElWRV9WU1lOQ19WUE9T X1NUQVJUX19TSElGVAkJCTAKK3N0YXRpYyBpbmxpbmUgdWludDMyX3QgRFNJX0FDVElWRV9WU1lO Q19WUE9TX1NUQVJUKHVpbnQzMl90IHZhbCkKK3sKKwlyZXR1cm4gKCh2YWwpIDw8IERTSV9BQ1RJ VkVfVlNZTkNfVlBPU19TVEFSVF9fU0hJRlQpICYgRFNJX0FDVElWRV9WU1lOQ19WUE9TX1NUQVJU X19NQVNLOworfQorI2RlZmluZSBEU0lfQUNUSVZFX1ZTWU5DX1ZQT1NfRU5EX19NQVNLCQkJCTB4 MGZmZjAwMDAKKyNkZWZpbmUgRFNJX0FDVElWRV9WU1lOQ19WUE9TX0VORF9fU0hJRlQJCQkxNgor c3RhdGljIGlubGluZSB1aW50MzJfdCBEU0lfQUNUSVZFX1ZTWU5DX1ZQT1NfRU5EKHVpbnQzMl90 IHZhbCkKK3sKKwlyZXR1cm4gKCh2YWwpIDw8IERTSV9BQ1RJVkVfVlNZTkNfVlBPU19FTkRfX1NI SUZUKSAmIERTSV9BQ1RJVkVfVlNZTkNfVlBPU19FTkRfX01BU0s7CiB9CiAKICNkZWZpbmUgUkVH X0RTSV9DTURfRE1BX0NUUkwJCQkJCTB4MDAwMDAwMzgKKyNkZWZpbmUgRFNJX0NNRF9ETUFfQ1RS TF9CUk9BRENBU1RfRU4JCQkJMHg4MDAwMDAwMAogI2RlZmluZSBEU0lfQ01EX0RNQV9DVFJMX0ZS T01fRlJBTUVfQlVGRkVSCQkJMHgxMDAwMDAwMAogI2RlZmluZSBEU0lfQ01EX0RNQV9DVFJMX0xP V19QT1dFUgkJCQkweDA0MDAwMDAwCiAKICNkZWZpbmUgUkVHX0RTSV9DTURfQ0ZHMAkJCQkJMHgw MDAwMDAzYworI2RlZmluZSBEU0lfQ01EX0NGRzBfRFNUX0ZPUk1BVF9fTUFTSwkJCQkweDAwMDAw MDBmCisjZGVmaW5lIERTSV9DTURfQ0ZHMF9EU1RfRk9STUFUX19TSElGVAkJCQkwCitzdGF0aWMg aW5saW5lIHVpbnQzMl90IERTSV9DTURfQ0ZHMF9EU1RfRk9STUFUKGVudW0gZHNpX2NtZF9kc3Rf Zm9ybWF0IHZhbCkKK3sKKwlyZXR1cm4gKCh2YWwpIDw8IERTSV9DTURfQ0ZHMF9EU1RfRk9STUFU X19TSElGVCkgJiBEU0lfQ01EX0NGRzBfRFNUX0ZPUk1BVF9fTUFTSzsKK30KKyNkZWZpbmUgRFNJ X0NNRF9DRkcwX1JfU0VMCQkJCQkweDAwMDAwMDEwCisjZGVmaW5lIERTSV9DTURfQ0ZHMF9HX1NF TAkJCQkJMHgwMDAwMDEwMAorI2RlZmluZSBEU0lfQ01EX0NGRzBfQl9TRUwJCQkJCTB4MDAwMDEw MDAKKyNkZWZpbmUgRFNJX0NNRF9DRkcwX0lOVEVSTEVBVkVfTUFYX19NQVNLCQkJMHgwMGYwMDAw MAorI2RlZmluZSBEU0lfQ01EX0NGRzBfSU5URVJMRUFWRV9NQVhfX1NISUZUCQkJMjAKK3N0YXRp YyBpbmxpbmUgdWludDMyX3QgRFNJX0NNRF9DRkcwX0lOVEVSTEVBVkVfTUFYKHVpbnQzMl90IHZh bCkKK3sKKwlyZXR1cm4gKCh2YWwpIDw8IERTSV9DTURfQ0ZHMF9JTlRFUkxFQVZFX01BWF9fU0hJ RlQpICYgRFNJX0NNRF9DRkcwX0lOVEVSTEVBVkVfTUFYX19NQVNLOworfQorI2RlZmluZSBEU0lf Q01EX0NGRzBfUkdCX1NXQVBfX01BU0sJCQkJMHgwMDA3MDAwMAorI2RlZmluZSBEU0lfQ01EX0NG RzBfUkdCX1NXQVBfX1NISUZUCQkJCTE2CitzdGF0aWMgaW5saW5lIHVpbnQzMl90IERTSV9DTURf Q0ZHMF9SR0JfU1dBUChlbnVtIGRzaV9yZ2Jfc3dhcCB2YWwpCit7CisJcmV0dXJuICgodmFsKSA8 PCBEU0lfQ01EX0NGRzBfUkdCX1NXQVBfX1NISUZUKSAmIERTSV9DTURfQ0ZHMF9SR0JfU1dBUF9f TUFTSzsKK30KIAogI2RlZmluZSBSRUdfRFNJX0NNRF9DRkcxCQkJCQkweDAwMDAwMDQwCisjZGVm aW5lIERTSV9DTURfQ0ZHMV9XUl9NRU1fU1RBUlRfX01BU0sJCQkJMHgwMDAwMDBmZgorI2RlZmlu ZSBEU0lfQ01EX0NGRzFfV1JfTUVNX1NUQVJUX19TSElGVAkJCTAKK3N0YXRpYyBpbmxpbmUgdWlu dDMyX3QgRFNJX0NNRF9DRkcxX1dSX01FTV9TVEFSVCh1aW50MzJfdCB2YWwpCit7CisJcmV0dXJu ICgodmFsKSA8PCBEU0lfQ01EX0NGRzFfV1JfTUVNX1NUQVJUX19TSElGVCkgJiBEU0lfQ01EX0NG RzFfV1JfTUVNX1NUQVJUX19NQVNLOworfQorI2RlZmluZSBEU0lfQ01EX0NGRzFfV1JfTUVNX0NP TlRJTlVFX19NQVNLCQkJMHgwMDAwZmYwMAorI2RlZmluZSBEU0lfQ01EX0NGRzFfV1JfTUVNX0NP TlRJTlVFX19TSElGVAkJCTgKK3N0YXRpYyBpbmxpbmUgdWludDMyX3QgRFNJX0NNRF9DRkcxX1dS X01FTV9DT05USU5VRSh1aW50MzJfdCB2YWwpCit7CisJcmV0dXJuICgodmFsKSA8PCBEU0lfQ01E X0NGRzFfV1JfTUVNX0NPTlRJTlVFX19TSElGVCkgJiBEU0lfQ01EX0NGRzFfV1JfTUVNX0NPTlRJ TlVFX19NQVNLOworfQorI2RlZmluZSBEU0lfQ01EX0NGRzFfSU5TRVJUX0RDU19DT01NQU5ECQkJ CTB4MDAwMTAwMDAKIAogI2RlZmluZSBSRUdfRFNJX0RNQV9CQVNFCQkJCQkweDAwMDAwMDQ0CiAK ICNkZWZpbmUgUkVHX0RTSV9ETUFfTEVOCQkJCQkJMHgwMDAwMDA0OAogCisjZGVmaW5lIFJFR19E U0lfQ01EX01EUF9TVFJFQU1fQ1RSTAkJCQkweDAwMDAwMDU0CisjZGVmaW5lIERTSV9DTURfTURQ X1NUUkVBTV9DVFJMX0RBVEFfVFlQRV9fTUFTSwkJCTB4MDAwMDAwM2YKKyNkZWZpbmUgRFNJX0NN RF9NRFBfU1RSRUFNX0NUUkxfREFUQV9UWVBFX19TSElGVAkJMAorc3RhdGljIGlubGluZSB1aW50 MzJfdCBEU0lfQ01EX01EUF9TVFJFQU1fQ1RSTF9EQVRBX1RZUEUodWludDMyX3QgdmFsKQorewor CXJldHVybiAoKHZhbCkgPDwgRFNJX0NNRF9NRFBfU1RSRUFNX0NUUkxfREFUQV9UWVBFX19TSElG VCkgJiBEU0lfQ01EX01EUF9TVFJFQU1fQ1RSTF9EQVRBX1RZUEVfX01BU0s7Cit9CisjZGVmaW5l IERTSV9DTURfTURQX1NUUkVBTV9DVFJMX1ZJUlRVQUxfQ0hBTk5FTF9fTUFTSwkJMHgwMDAwMDMw MAorI2RlZmluZSBEU0lfQ01EX01EUF9TVFJFQU1fQ1RSTF9WSVJUVUFMX0NIQU5ORUxfX1NISUZU CQk4CitzdGF0aWMgaW5saW5lIHVpbnQzMl90IERTSV9DTURfTURQX1NUUkVBTV9DVFJMX1ZJUlRV QUxfQ0hBTk5FTCh1aW50MzJfdCB2YWwpCit7CisJcmV0dXJuICgodmFsKSA8PCBEU0lfQ01EX01E UF9TVFJFQU1fQ1RSTF9WSVJUVUFMX0NIQU5ORUxfX1NISUZUKSAmIERTSV9DTURfTURQX1NUUkVB TV9DVFJMX1ZJUlRVQUxfQ0hBTk5FTF9fTUFTSzsKK30KKyNkZWZpbmUgRFNJX0NNRF9NRFBfU1RS RUFNX0NUUkxfV09SRF9DT1VOVF9fTUFTSwkJMHhmZmZmMDAwMAorI2RlZmluZSBEU0lfQ01EX01E UF9TVFJFQU1fQ1RSTF9XT1JEX0NPVU5UX19TSElGVAkJMTYKK3N0YXRpYyBpbmxpbmUgdWludDMy X3QgRFNJX0NNRF9NRFBfU1RSRUFNX0NUUkxfV09SRF9DT1VOVCh1aW50MzJfdCB2YWwpCit7CisJ cmV0dXJuICgodmFsKSA8PCBEU0lfQ01EX01EUF9TVFJFQU1fQ1RSTF9XT1JEX0NPVU5UX19TSElG VCkgJiBEU0lfQ01EX01EUF9TVFJFQU1fQ1RSTF9XT1JEX0NPVU5UX19NQVNLOworfQorCisjZGVm aW5lIFJFR19EU0lfQ01EX01EUF9TVFJFQU1fVE9UQUwJCQkJMHgwMDAwMDA1OAorI2RlZmluZSBE U0lfQ01EX01EUF9TVFJFQU1fVE9UQUxfSF9UT1RBTF9fTUFTSwkJCTB4MDAwMDBmZmYKKyNkZWZp bmUgRFNJX0NNRF9NRFBfU1RSRUFNX1RPVEFMX0hfVE9UQUxfX1NISUZUCQkJMAorc3RhdGljIGlu bGluZSB1aW50MzJfdCBEU0lfQ01EX01EUF9TVFJFQU1fVE9UQUxfSF9UT1RBTCh1aW50MzJfdCB2 YWwpCit7CisJcmV0dXJuICgodmFsKSA8PCBEU0lfQ01EX01EUF9TVFJFQU1fVE9UQUxfSF9UT1RB TF9fU0hJRlQpICYgRFNJX0NNRF9NRFBfU1RSRUFNX1RPVEFMX0hfVE9UQUxfX01BU0s7Cit9Cisj ZGVmaW5lIERTSV9DTURfTURQX1NUUkVBTV9UT1RBTF9WX1RPVEFMX19NQVNLCQkJMHgwZmZmMDAw MAorI2RlZmluZSBEU0lfQ01EX01EUF9TVFJFQU1fVE9UQUxfVl9UT1RBTF9fU0hJRlQJCQkxNgor c3RhdGljIGlubGluZSB1aW50MzJfdCBEU0lfQ01EX01EUF9TVFJFQU1fVE9UQUxfVl9UT1RBTCh1 aW50MzJfdCB2YWwpCit7CisJcmV0dXJuICgodmFsKSA8PCBEU0lfQ01EX01EUF9TVFJFQU1fVE9U QUxfVl9UT1RBTF9fU0hJRlQpICYgRFNJX0NNRF9NRFBfU1RSRUFNX1RPVEFMX1ZfVE9UQUxfX01B U0s7Cit9CisKICNkZWZpbmUgUkVHX0RTSV9BQ0tfRVJSX1NUQVRVUwkJCQkJMHgwMDAwMDA2NAog CiBzdGF0aWMgaW5saW5lIHVpbnQzMl90IFJFR19EU0lfUkRCSyh1aW50MzJfdCBpMCkgeyByZXR1 cm4gMHgwMDAwMDA2OCArIDB4NCppMDsgfQpAQCAtMjM0LDE5ICszNDksMjUgQEAgc3RhdGljIGlu bGluZSB1aW50MzJfdCBSRUdfRFNJX1JEQksodWludDMyX3QgaTApIHsgcmV0dXJuIDB4MDAwMDAw NjggKyAweDQqaTA7IH0KIHN0YXRpYyBpbmxpbmUgdWludDMyX3QgUkVHX0RTSV9SREJLX0RBVEEo dWludDMyX3QgaTApIHsgcmV0dXJuIDB4MDAwMDAwNjggKyAweDQqaTA7IH0KIAogI2RlZmluZSBS RUdfRFNJX1RSSUdfQ1RSTAkJCQkJMHgwMDAwMDA4MAotI2RlZmluZSBEU0lfVFJJR19DVFJMX0RN QV9UUklHR0VSX19NQVNLCQkJCTB4MDAwMDAwMGYKKyNkZWZpbmUgRFNJX1RSSUdfQ1RSTF9ETUFf VFJJR0dFUl9fTUFTSwkJCQkweDAwMDAwMDA3CiAjZGVmaW5lIERTSV9UUklHX0NUUkxfRE1BX1RS SUdHRVJfX1NISUZUCQkJMAogc3RhdGljIGlubGluZSB1aW50MzJfdCBEU0lfVFJJR19DVFJMX0RN QV9UUklHR0VSKGVudW0gZHNpX2NtZF90cmlnZ2VyIHZhbCkKIHsKIAlyZXR1cm4gKCh2YWwpIDw8 IERTSV9UUklHX0NUUkxfRE1BX1RSSUdHRVJfX1NISUZUKSAmIERTSV9UUklHX0NUUkxfRE1BX1RS SUdHRVJfX01BU0s7CiB9Ci0jZGVmaW5lIERTSV9UUklHX0NUUkxfTURQX1RSSUdHRVJfX01BU0sJ CQkJMHgwMDAwMDBmMAorI2RlZmluZSBEU0lfVFJJR19DVFJMX01EUF9UUklHR0VSX19NQVNLCQkJ CTB4MDAwMDAwNzAKICNkZWZpbmUgRFNJX1RSSUdfQ1RSTF9NRFBfVFJJR0dFUl9fU0hJRlQJCQk0 CiBzdGF0aWMgaW5saW5lIHVpbnQzMl90IERTSV9UUklHX0NUUkxfTURQX1RSSUdHRVIoZW51bSBk c2lfY21kX3RyaWdnZXIgdmFsKQogewogCXJldHVybiAoKHZhbCkgPDwgRFNJX1RSSUdfQ1RSTF9N RFBfVFJJR0dFUl9fU0hJRlQpICYgRFNJX1RSSUdfQ1RSTF9NRFBfVFJJR0dFUl9fTUFTSzsKIH0K LSNkZWZpbmUgRFNJX1RSSUdfQ1RSTF9TVFJFQU0JCQkJCTB4MDAwMDAxMDAKKyNkZWZpbmUgRFNJ X1RSSUdfQ1RSTF9TVFJFQU1fX01BU0sJCQkJMHgwMDAwMDMwMAorI2RlZmluZSBEU0lfVFJJR19D VFJMX1NUUkVBTV9fU0hJRlQJCQkJOAorc3RhdGljIGlubGluZSB1aW50MzJfdCBEU0lfVFJJR19D VFJMX1NUUkVBTSh1aW50MzJfdCB2YWwpCit7CisJcmV0dXJuICgodmFsKSA8PCBEU0lfVFJJR19D VFJMX1NUUkVBTV9fU0hJRlQpICYgRFNJX1RSSUdfQ1RSTF9TVFJFQU1fX01BU0s7Cit9CisjZGVm aW5lIERTSV9UUklHX0NUUkxfQkxPQ0tfRE1BX1dJVEhJTl9GUkFNRQkJCTB4MDAwMDEwMDAKICNk ZWZpbmUgRFNJX1RSSUdfQ1RSTF9URQkJCQkJMHg4MDAwMDAwMAogCiAjZGVmaW5lIFJFR19EU0lf VFJJR19ETUEJCQkJCTB4MDAwMDAwOGMKQEAgLTI3NCw2ICszOTUsMTIgQEAgc3RhdGljIGlubGlu ZSB1aW50MzJfdCBEU0lfQ0xLT1VUX1RJTUlOR19DVFJMX1RfQ0xLX1BPU1QodWludDMyX3QgdmFs KQogI2RlZmluZSBEU0lfRU9UX1BBQ0tFVF9DVFJMX1JYX0VPVF9JR05PUkUJCQkweDAwMDAwMDEw CiAKICNkZWZpbmUgUkVHX0RTSV9MQU5FX1NXQVBfQ1RSTAkJCQkJMHgwMDAwMDBhYworI2RlZmlu ZSBEU0lfTEFORV9TV0FQX0NUUkxfRExOX1NXQVBfU0VMX19NQVNLCQkJMHgwMDAwMDAwNworI2Rl ZmluZSBEU0lfTEFORV9TV0FQX0NUUkxfRExOX1NXQVBfU0VMX19TSElGVAkJCTAKK3N0YXRpYyBp bmxpbmUgdWludDMyX3QgRFNJX0xBTkVfU1dBUF9DVFJMX0RMTl9TV0FQX1NFTChlbnVtIGRzaV9s YW5lX3N3YXAgdmFsKQoreworCXJldHVybiAoKHZhbCkgPDwgRFNJX0xBTkVfU1dBUF9DVFJMX0RM Tl9TV0FQX1NFTF9fU0hJRlQpICYgRFNJX0xBTkVfU1dBUF9DVFJMX0RMTl9TV0FQX1NFTF9fTUFT SzsKK30KIAogI2RlZmluZSBSRUdfRFNJX0VSUl9JTlRfTUFTSzAJCQkJCTB4MDAwMDAxMDgKIApA QCAtMjgyLDggKzQwOSwzNiBAQCBzdGF0aWMgaW5saW5lIHVpbnQzMl90IERTSV9DTEtPVVRfVElN SU5HX0NUUkxfVF9DTEtfUE9TVCh1aW50MzJfdCB2YWwpCiAjZGVmaW5lIFJFR19EU0lfUkVTRVQJ CQkJCQkweDAwMDAwMTE0CiAKICNkZWZpbmUgUkVHX0RTSV9DTEtfQ1RSTAkJCQkJMHgwMDAwMDEx OAorI2RlZmluZSBEU0lfQ0xLX0NUUkxfQUhCU19IQ0xLX09OCQkJCTB4MDAwMDAwMDEKKyNkZWZp bmUgRFNJX0NMS19DVFJMX0FIQk1fU0NMS19PTgkJCQkweDAwMDAwMDAyCisjZGVmaW5lIERTSV9D TEtfQ1RSTF9QQ0xLX09OCQkJCQkweDAwMDAwMDA0CisjZGVmaW5lIERTSV9DTEtfQ1RSTF9EU0lD TEtfT04JCQkJCTB4MDAwMDAwMDgKKyNkZWZpbmUgRFNJX0NMS19DVFJMX0JZVEVDTEtfT04JCQkJ CTB4MDAwMDAwMTAKKyNkZWZpbmUgRFNJX0NMS19DVFJMX0VTQ0NMS19PTgkJCQkJMHgwMDAwMDAy MAorI2RlZmluZSBEU0lfQ0xLX0NUUkxfRk9SQ0VfT05fRFlOX0FIQk1fSENMSwkJCTB4MDAwMDAy MDAKKworI2RlZmluZSBSRUdfRFNJX0NMS19TVEFUVVMJCQkJCTB4MDAwMDAxMWMKKyNkZWZpbmUg RFNJX0NMS19TVEFUVVNfUExMX1VOTE9DS0VECQkJCTB4MDAwMTAwMDAKIAogI2RlZmluZSBSRUdf RFNJX1BIWV9SRVNFVAkJCQkJMHgwMDAwMDEyOAorI2RlZmluZSBEU0lfUEhZX1JFU0VUX1JFU0VU CQkJCQkweDAwMDAwMDAxCisKKyNkZWZpbmUgUkVHX0RTSV9SREJLX0RBVEFfQ1RSTAkJCQkJMHgw MDAwMDFkMAorI2RlZmluZSBEU0lfUkRCS19EQVRBX0NUUkxfQ09VTlRfX01BU0sJCQkJMHgwMGZm MDAwMAorI2RlZmluZSBEU0lfUkRCS19EQVRBX0NUUkxfQ09VTlRfX1NISUZUCQkJCTE2CitzdGF0 aWMgaW5saW5lIHVpbnQzMl90IERTSV9SREJLX0RBVEFfQ1RSTF9DT1VOVCh1aW50MzJfdCB2YWwp Cit7CisJcmV0dXJuICgodmFsKSA8PCBEU0lfUkRCS19EQVRBX0NUUkxfQ09VTlRfX1NISUZUKSAm IERTSV9SREJLX0RBVEFfQ1RSTF9DT1VOVF9fTUFTSzsKK30KKyNkZWZpbmUgRFNJX1JEQktfREFU QV9DVFJMX0NMUgkJCQkJMHgwMDAwMDAwMQorCisjZGVmaW5lIFJFR19EU0lfVkVSU0lPTgkJCQkJ CTB4MDAwMDAxZjAKKyNkZWZpbmUgRFNJX1ZFUlNJT05fTUFKT1JfX01BU0sJCQkJCTB4ZmYwMDAw MDAKKyNkZWZpbmUgRFNJX1ZFUlNJT05fTUFKT1JfX1NISUZUCQkJCTI0CitzdGF0aWMgaW5saW5l IHVpbnQzMl90IERTSV9WRVJTSU9OX01BSk9SKHVpbnQzMl90IHZhbCkKK3sKKwlyZXR1cm4gKCh2 YWwpIDw8IERTSV9WRVJTSU9OX01BSk9SX19TSElGVCkgJiBEU0lfVkVSU0lPTl9NQUpPUl9fTUFT SzsKK30KIAogI2RlZmluZSBSRUdfRFNJX1BIWV9QTExfQ1RSTF8wCQkJCQkweDAwMDAwMjAwCiAj ZGVmaW5lIERTSV9QSFlfUExMX0NUUkxfMF9FTkFCTEUJCQkJMHgwMDAwMDAwMQpAQCAtNTAxLDUg KzY1NiwxODQgQEAgc3RhdGljIGlubGluZSB1aW50MzJfdCBSRUdfRFNJXzg5NjBfTE5fVEVTVF9T VFJfMSh1aW50MzJfdCBpMCkgeyByZXR1cm4gMHgwMDAwMDMKICNkZWZpbmUgUkVHX0RTSV84OTYw X1BIWV9DQUxfU1RBVFVTCQkJCTB4MDAwMDA1NTAKICNkZWZpbmUgRFNJXzg5NjBfUEhZX0NBTF9T VEFUVVNfQ0FMX0JVU1kJCQkweDAwMDAwMDEwCiAKK3N0YXRpYyBpbmxpbmUgdWludDMyX3QgUkVH X0RTSV8yOG5tX1BIWV9MTih1aW50MzJfdCBpMCkgeyByZXR1cm4gMHgwMDAwMDAwMCArIDB4NDAq aTA7IH0KKworc3RhdGljIGlubGluZSB1aW50MzJfdCBSRUdfRFNJXzI4bm1fUEhZX0xOX0NGR18w KHVpbnQzMl90IGkwKSB7IHJldHVybiAweDAwMDAwMDAwICsgMHg0MCppMDsgfQorCitzdGF0aWMg aW5saW5lIHVpbnQzMl90IFJFR19EU0lfMjhubV9QSFlfTE5fQ0ZHXzEodWludDMyX3QgaTApIHsg cmV0dXJuIDB4MDAwMDAwMDQgKyAweDQwKmkwOyB9CisKK3N0YXRpYyBpbmxpbmUgdWludDMyX3Qg UkVHX0RTSV8yOG5tX1BIWV9MTl9DRkdfMih1aW50MzJfdCBpMCkgeyByZXR1cm4gMHgwMDAwMDAw OCArIDB4NDAqaTA7IH0KKworc3RhdGljIGlubGluZSB1aW50MzJfdCBSRUdfRFNJXzI4bm1fUEhZ X0xOX0NGR18zKHVpbnQzMl90IGkwKSB7IHJldHVybiAweDAwMDAwMDBjICsgMHg0MCppMDsgfQor CitzdGF0aWMgaW5saW5lIHVpbnQzMl90IFJFR19EU0lfMjhubV9QSFlfTE5fQ0ZHXzQodWludDMy X3QgaTApIHsgcmV0dXJuIDB4MDAwMDAwMTAgKyAweDQwKmkwOyB9CisKK3N0YXRpYyBpbmxpbmUg dWludDMyX3QgUkVHX0RTSV8yOG5tX1BIWV9MTl9URVNUX0RBVEFQQVRIKHVpbnQzMl90IGkwKSB7 IHJldHVybiAweDAwMDAwMDE0ICsgMHg0MCppMDsgfQorCitzdGF0aWMgaW5saW5lIHVpbnQzMl90 IFJFR19EU0lfMjhubV9QSFlfTE5fREVCVUdfU0VMKHVpbnQzMl90IGkwKSB7IHJldHVybiAweDAw MDAwMDE4ICsgMHg0MCppMDsgfQorCitzdGF0aWMgaW5saW5lIHVpbnQzMl90IFJFR19EU0lfMjhu bV9QSFlfTE5fVEVTVF9TVFJfMCh1aW50MzJfdCBpMCkgeyByZXR1cm4gMHgwMDAwMDAxYyArIDB4 NDAqaTA7IH0KKworc3RhdGljIGlubGluZSB1aW50MzJfdCBSRUdfRFNJXzI4bm1fUEhZX0xOX1RF U1RfU1RSXzEodWludDMyX3QgaTApIHsgcmV0dXJuIDB4MDAwMDAwMjAgKyAweDQwKmkwOyB9CisK KyNkZWZpbmUgUkVHX0RTSV8yOG5tX1BIWV9MTkNLX0NGR18wCQkJCTB4MDAwMDAxMDAKKworI2Rl ZmluZSBSRUdfRFNJXzI4bm1fUEhZX0xOQ0tfQ0ZHXzEJCQkJMHgwMDAwMDEwNAorCisjZGVmaW5l IFJFR19EU0lfMjhubV9QSFlfTE5DS19DRkdfMgkJCQkweDAwMDAwMTA4CisKKyNkZWZpbmUgUkVH X0RTSV8yOG5tX1BIWV9MTkNLX0NGR18zCQkJCTB4MDAwMDAxMGMKKworI2RlZmluZSBSRUdfRFNJ XzI4bm1fUEhZX0xOQ0tfQ0ZHXzQJCQkJMHgwMDAwMDExMAorCisjZGVmaW5lIFJFR19EU0lfMjhu bV9QSFlfTE5DS19URVNUX0RBVEFQQVRICQkJMHgwMDAwMDExNAorCisjZGVmaW5lIFJFR19EU0lf MjhubV9QSFlfTE5DS19ERUJVR19TRUwJCQkJMHgwMDAwMDExOAorCisjZGVmaW5lIFJFR19EU0lf MjhubV9QSFlfTE5DS19URVNUX1NUUjAJCQkJMHgwMDAwMDExYworCisjZGVmaW5lIFJFR19EU0lf MjhubV9QSFlfTE5DS19URVNUX1NUUjEJCQkJMHgwMDAwMDEyMAorCisjZGVmaW5lIFJFR19EU0lf MjhubV9QSFlfVElNSU5HX0NUUkxfMAkJCQkweDAwMDAwMTQwCisjZGVmaW5lIERTSV8yOG5tX1BI WV9USU1JTkdfQ1RSTF8wX0NMS19aRVJPX19NQVNLCQkweDAwMDAwMGZmCisjZGVmaW5lIERTSV8y OG5tX1BIWV9USU1JTkdfQ1RSTF8wX0NMS19aRVJPX19TSElGVAkJMAorc3RhdGljIGlubGluZSB1 aW50MzJfdCBEU0lfMjhubV9QSFlfVElNSU5HX0NUUkxfMF9DTEtfWkVSTyh1aW50MzJfdCB2YWwp Cit7CisJcmV0dXJuICgodmFsKSA8PCBEU0lfMjhubV9QSFlfVElNSU5HX0NUUkxfMF9DTEtfWkVS T19fU0hJRlQpICYgRFNJXzI4bm1fUEhZX1RJTUlOR19DVFJMXzBfQ0xLX1pFUk9fX01BU0s7Cit9 CisKKyNkZWZpbmUgUkVHX0RTSV8yOG5tX1BIWV9USU1JTkdfQ1RSTF8xCQkJCTB4MDAwMDAxNDQK KyNkZWZpbmUgRFNJXzI4bm1fUEhZX1RJTUlOR19DVFJMXzFfQ0xLX1RSQUlMX19NQVNLCQkweDAw MDAwMGZmCisjZGVmaW5lIERTSV8yOG5tX1BIWV9USU1JTkdfQ1RSTF8xX0NMS19UUkFJTF9fU0hJ RlQJCTAKK3N0YXRpYyBpbmxpbmUgdWludDMyX3QgRFNJXzI4bm1fUEhZX1RJTUlOR19DVFJMXzFf Q0xLX1RSQUlMKHVpbnQzMl90IHZhbCkKK3sKKwlyZXR1cm4gKCh2YWwpIDw8IERTSV8yOG5tX1BI WV9USU1JTkdfQ1RSTF8xX0NMS19UUkFJTF9fU0hJRlQpICYgRFNJXzI4bm1fUEhZX1RJTUlOR19D VFJMXzFfQ0xLX1RSQUlMX19NQVNLOworfQorCisjZGVmaW5lIFJFR19EU0lfMjhubV9QSFlfVElN SU5HX0NUUkxfMgkJCQkweDAwMDAwMTQ4CisjZGVmaW5lIERTSV8yOG5tX1BIWV9USU1JTkdfQ1RS TF8yX0NMS19QUkVQQVJFX19NQVNLCQkweDAwMDAwMGZmCisjZGVmaW5lIERTSV8yOG5tX1BIWV9U SU1JTkdfQ1RSTF8yX0NMS19QUkVQQVJFX19TSElGVAkJMAorc3RhdGljIGlubGluZSB1aW50MzJf dCBEU0lfMjhubV9QSFlfVElNSU5HX0NUUkxfMl9DTEtfUFJFUEFSRSh1aW50MzJfdCB2YWwpCit7 CisJcmV0dXJuICgodmFsKSA8PCBEU0lfMjhubV9QSFlfVElNSU5HX0NUUkxfMl9DTEtfUFJFUEFS RV9fU0hJRlQpICYgRFNJXzI4bm1fUEhZX1RJTUlOR19DVFJMXzJfQ0xLX1BSRVBBUkVfX01BU0s7 Cit9CisKKyNkZWZpbmUgUkVHX0RTSV8yOG5tX1BIWV9USU1JTkdfQ1RSTF8zCQkJCTB4MDAwMDAx NGMKKyNkZWZpbmUgRFNJXzI4bm1fUEhZX1RJTUlOR19DVFJMXzNfQ0xLX1pFUk9fOAkJCTB4MDAw MDAwMDEKKworI2RlZmluZSBSRUdfRFNJXzI4bm1fUEhZX1RJTUlOR19DVFJMXzQJCQkJMHgwMDAw MDE1MAorI2RlZmluZSBEU0lfMjhubV9QSFlfVElNSU5HX0NUUkxfNF9IU19FWElUX19NQVNLCQkw eDAwMDAwMGZmCisjZGVmaW5lIERTSV8yOG5tX1BIWV9USU1JTkdfQ1RSTF80X0hTX0VYSVRfX1NI SUZUCQkwCitzdGF0aWMgaW5saW5lIHVpbnQzMl90IERTSV8yOG5tX1BIWV9USU1JTkdfQ1RSTF80 X0hTX0VYSVQodWludDMyX3QgdmFsKQoreworCXJldHVybiAoKHZhbCkgPDwgRFNJXzI4bm1fUEhZ X1RJTUlOR19DVFJMXzRfSFNfRVhJVF9fU0hJRlQpICYgRFNJXzI4bm1fUEhZX1RJTUlOR19DVFJM XzRfSFNfRVhJVF9fTUFTSzsKK30KKworI2RlZmluZSBSRUdfRFNJXzI4bm1fUEhZX1RJTUlOR19D VFJMXzUJCQkJMHgwMDAwMDE1NAorI2RlZmluZSBEU0lfMjhubV9QSFlfVElNSU5HX0NUUkxfNV9I U19aRVJPX19NQVNLCQkweDAwMDAwMGZmCisjZGVmaW5lIERTSV8yOG5tX1BIWV9USU1JTkdfQ1RS TF81X0hTX1pFUk9fX1NISUZUCQkwCitzdGF0aWMgaW5saW5lIHVpbnQzMl90IERTSV8yOG5tX1BI WV9USU1JTkdfQ1RSTF81X0hTX1pFUk8odWludDMyX3QgdmFsKQoreworCXJldHVybiAoKHZhbCkg PDwgRFNJXzI4bm1fUEhZX1RJTUlOR19DVFJMXzVfSFNfWkVST19fU0hJRlQpICYgRFNJXzI4bm1f UEhZX1RJTUlOR19DVFJMXzVfSFNfWkVST19fTUFTSzsKK30KKworI2RlZmluZSBSRUdfRFNJXzI4 bm1fUEhZX1RJTUlOR19DVFJMXzYJCQkJMHgwMDAwMDE1OAorI2RlZmluZSBEU0lfMjhubV9QSFlf VElNSU5HX0NUUkxfNl9IU19QUkVQQVJFX19NQVNLCQkweDAwMDAwMGZmCisjZGVmaW5lIERTSV8y OG5tX1BIWV9USU1JTkdfQ1RSTF82X0hTX1BSRVBBUkVfX1NISUZUCQkwCitzdGF0aWMgaW5saW5l IHVpbnQzMl90IERTSV8yOG5tX1BIWV9USU1JTkdfQ1RSTF82X0hTX1BSRVBBUkUodWludDMyX3Qg dmFsKQoreworCXJldHVybiAoKHZhbCkgPDwgRFNJXzI4bm1fUEhZX1RJTUlOR19DVFJMXzZfSFNf UFJFUEFSRV9fU0hJRlQpICYgRFNJXzI4bm1fUEhZX1RJTUlOR19DVFJMXzZfSFNfUFJFUEFSRV9f TUFTSzsKK30KKworI2RlZmluZSBSRUdfRFNJXzI4bm1fUEhZX1RJTUlOR19DVFJMXzcJCQkJMHgw MDAwMDE1YworI2RlZmluZSBEU0lfMjhubV9QSFlfVElNSU5HX0NUUkxfN19IU19UUkFJTF9fTUFT SwkJMHgwMDAwMDBmZgorI2RlZmluZSBEU0lfMjhubV9QSFlfVElNSU5HX0NUUkxfN19IU19UUkFJ TF9fU0hJRlQJCTAKK3N0YXRpYyBpbmxpbmUgdWludDMyX3QgRFNJXzI4bm1fUEhZX1RJTUlOR19D VFJMXzdfSFNfVFJBSUwodWludDMyX3QgdmFsKQoreworCXJldHVybiAoKHZhbCkgPDwgRFNJXzI4 bm1fUEhZX1RJTUlOR19DVFJMXzdfSFNfVFJBSUxfX1NISUZUKSAmIERTSV8yOG5tX1BIWV9USU1J TkdfQ1RSTF83X0hTX1RSQUlMX19NQVNLOworfQorCisjZGVmaW5lIFJFR19EU0lfMjhubV9QSFlf VElNSU5HX0NUUkxfOAkJCQkweDAwMDAwMTYwCisjZGVmaW5lIERTSV8yOG5tX1BIWV9USU1JTkdf Q1RSTF84X0hTX1JRU1RfX01BU0sJCTB4MDAwMDAwZmYKKyNkZWZpbmUgRFNJXzI4bm1fUEhZX1RJ TUlOR19DVFJMXzhfSFNfUlFTVF9fU0hJRlQJCTAKK3N0YXRpYyBpbmxpbmUgdWludDMyX3QgRFNJ XzI4bm1fUEhZX1RJTUlOR19DVFJMXzhfSFNfUlFTVCh1aW50MzJfdCB2YWwpCit7CisJcmV0dXJu ICgodmFsKSA8PCBEU0lfMjhubV9QSFlfVElNSU5HX0NUUkxfOF9IU19SUVNUX19TSElGVCkgJiBE U0lfMjhubV9QSFlfVElNSU5HX0NUUkxfOF9IU19SUVNUX19NQVNLOworfQorCisjZGVmaW5lIFJF R19EU0lfMjhubV9QSFlfVElNSU5HX0NUUkxfOQkJCQkweDAwMDAwMTY0CisjZGVmaW5lIERTSV8y OG5tX1BIWV9USU1JTkdfQ1RSTF85X1RBX0dPX19NQVNLCQkJMHgwMDAwMDAwNworI2RlZmluZSBE U0lfMjhubV9QSFlfVElNSU5HX0NUUkxfOV9UQV9HT19fU0hJRlQJCQkwCitzdGF0aWMgaW5saW5l IHVpbnQzMl90IERTSV8yOG5tX1BIWV9USU1JTkdfQ1RSTF85X1RBX0dPKHVpbnQzMl90IHZhbCkK K3sKKwlyZXR1cm4gKCh2YWwpIDw8IERTSV8yOG5tX1BIWV9USU1JTkdfQ1RSTF85X1RBX0dPX19T SElGVCkgJiBEU0lfMjhubV9QSFlfVElNSU5HX0NUUkxfOV9UQV9HT19fTUFTSzsKK30KKyNkZWZp bmUgRFNJXzI4bm1fUEhZX1RJTUlOR19DVFJMXzlfVEFfU1VSRV9fTUFTSwkJMHgwMDAwMDA3MAor I2RlZmluZSBEU0lfMjhubV9QSFlfVElNSU5HX0NUUkxfOV9UQV9TVVJFX19TSElGVAkJNAorc3Rh dGljIGlubGluZSB1aW50MzJfdCBEU0lfMjhubV9QSFlfVElNSU5HX0NUUkxfOV9UQV9TVVJFKHVp bnQzMl90IHZhbCkKK3sKKwlyZXR1cm4gKCh2YWwpIDw8IERTSV8yOG5tX1BIWV9USU1JTkdfQ1RS TF85X1RBX1NVUkVfX1NISUZUKSAmIERTSV8yOG5tX1BIWV9USU1JTkdfQ1RSTF85X1RBX1NVUkVf X01BU0s7Cit9CisKKyNkZWZpbmUgUkVHX0RTSV8yOG5tX1BIWV9USU1JTkdfQ1RSTF8xMAkJCQkw eDAwMDAwMTY4CisjZGVmaW5lIERTSV8yOG5tX1BIWV9USU1JTkdfQ1RSTF8xMF9UQV9HRVRfX01B U0sJCTB4MDAwMDAwMDcKKyNkZWZpbmUgRFNJXzI4bm1fUEhZX1RJTUlOR19DVFJMXzEwX1RBX0dF VF9fU0hJRlQJCTAKK3N0YXRpYyBpbmxpbmUgdWludDMyX3QgRFNJXzI4bm1fUEhZX1RJTUlOR19D VFJMXzEwX1RBX0dFVCh1aW50MzJfdCB2YWwpCit7CisJcmV0dXJuICgodmFsKSA8PCBEU0lfMjhu bV9QSFlfVElNSU5HX0NUUkxfMTBfVEFfR0VUX19TSElGVCkgJiBEU0lfMjhubV9QSFlfVElNSU5H X0NUUkxfMTBfVEFfR0VUX19NQVNLOworfQorCisjZGVmaW5lIFJFR19EU0lfMjhubV9QSFlfVElN SU5HX0NUUkxfMTEJCQkJMHgwMDAwMDE2YworI2RlZmluZSBEU0lfMjhubV9QSFlfVElNSU5HX0NU UkxfMTFfVFJJRzNfQ01EX19NQVNLCQkweDAwMDAwMGZmCisjZGVmaW5lIERTSV8yOG5tX1BIWV9U SU1JTkdfQ1RSTF8xMV9UUklHM19DTURfX1NISUZUCQkwCitzdGF0aWMgaW5saW5lIHVpbnQzMl90 IERTSV8yOG5tX1BIWV9USU1JTkdfQ1RSTF8xMV9UUklHM19DTUQodWludDMyX3QgdmFsKQorewor CXJldHVybiAoKHZhbCkgPDwgRFNJXzI4bm1fUEhZX1RJTUlOR19DVFJMXzExX1RSSUczX0NNRF9f U0hJRlQpICYgRFNJXzI4bm1fUEhZX1RJTUlOR19DVFJMXzExX1RSSUczX0NNRF9fTUFTSzsKK30K KworI2RlZmluZSBSRUdfRFNJXzI4bm1fUEhZX0NUUkxfMAkJCQkJMHgwMDAwMDE3MAorCisjZGVm aW5lIFJFR19EU0lfMjhubV9QSFlfQ1RSTF8xCQkJCQkweDAwMDAwMTc0CisKKyNkZWZpbmUgUkVH X0RTSV8yOG5tX1BIWV9DVFJMXzIJCQkJCTB4MDAwMDAxNzgKKworI2RlZmluZSBSRUdfRFNJXzI4 bm1fUEhZX0NUUkxfMwkJCQkJMHgwMDAwMDE3YworCisjZGVmaW5lIFJFR19EU0lfMjhubV9QSFlf Q1RSTF80CQkJCQkweDAwMDAwMTgwCisKKyNkZWZpbmUgUkVHX0RTSV8yOG5tX1BIWV9TVFJFTkdU SF8wCQkJCTB4MDAwMDAxODQKKworI2RlZmluZSBSRUdfRFNJXzI4bm1fUEhZX1NUUkVOR1RIXzEJ CQkJMHgwMDAwMDE4OAorCisjZGVmaW5lIFJFR19EU0lfMjhubV9QSFlfQklTVF9DVFJMXzAJCQkJ MHgwMDAwMDFiNAorCisjZGVmaW5lIFJFR19EU0lfMjhubV9QSFlfQklTVF9DVFJMXzEJCQkJMHgw MDAwMDFiOAorCisjZGVmaW5lIFJFR19EU0lfMjhubV9QSFlfQklTVF9DVFJMXzIJCQkJMHgwMDAw MDFiYworCisjZGVmaW5lIFJFR19EU0lfMjhubV9QSFlfQklTVF9DVFJMXzMJCQkJMHgwMDAwMDFj MAorCisjZGVmaW5lIFJFR19EU0lfMjhubV9QSFlfQklTVF9DVFJMXzQJCQkJMHgwMDAwMDFjNAor CisjZGVmaW5lIFJFR19EU0lfMjhubV9QSFlfQklTVF9DVFJMXzUJCQkJMHgwMDAwMDFjOAorCisj ZGVmaW5lIFJFR19EU0lfMjhubV9QSFlfR0xCTF9URVNUX0NUUkwJCQkJMHgwMDAwMDFkNAorCisj ZGVmaW5lIFJFR19EU0lfMjhubV9QSFlfTERPX0NOVFJMCQkJCTB4MDAwMDAxZGMKKworI2RlZmlu ZSBSRUdfRFNJXzI4bm1fUEhZX1JFR1VMQVRPUl9DVFJMXzAJCQkweDAwMDAwMDAwCisKKyNkZWZp bmUgUkVHX0RTSV8yOG5tX1BIWV9SRUdVTEFUT1JfQ1RSTF8xCQkJMHgwMDAwMDAwNAorCisjZGVm aW5lIFJFR19EU0lfMjhubV9QSFlfUkVHVUxBVE9SX0NUUkxfMgkJCTB4MDAwMDAwMDgKKworI2Rl ZmluZSBSRUdfRFNJXzI4bm1fUEhZX1JFR1VMQVRPUl9DVFJMXzMJCQkweDAwMDAwMDBjCisKKyNk ZWZpbmUgUkVHX0RTSV8yOG5tX1BIWV9SRUdVTEFUT1JfQ1RSTF80CQkJMHgwMDAwMDAxMAorCisj ZGVmaW5lIFJFR19EU0lfMjhubV9QSFlfUkVHVUxBVE9SX0NUUkxfNQkJCTB4MDAwMDAwMTQKKwor I2RlZmluZSBSRUdfRFNJXzI4bm1fUEhZX1JFR1VMQVRPUl9DQUxfUFdSX0NGRwkJCTB4MDAwMDAw MTgKKwogCiAjZW5kaWYgLyogRFNJX1hNTCAqLwotLSAKVGhlIFF1YWxjb21tIElubm92YXRpb24g Q2VudGVyLCBJbmMuIGlzIGEgbWVtYmVyIG9mIHRoZSBDb2RlIEF1cm9yYSBGb3J1bSwKaG9zdGVk IGJ5IFRoZSBMaW51eCBGb3VuZGF0aW9uCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5m cmVlZGVza3RvcC5vcmcKaHR0cDovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3Rp bmZvL2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756619AbbCMXYv (ORCPT ); Fri, 13 Mar 2015 19:24:51 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:45673 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755399AbbCMXYr (ORCPT ); Fri, 13 Mar 2015 19:24:47 -0400 From: Hai Li To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, robdclark@gmail.com, Hai Li Subject: [PATCH 1/4] drm/msm/dsi: Update generated DSI header file Date: Fri, 13 Mar 2015 19:24:15 -0400 Message-Id: <1426289058-6663-2-git-send-email-hali@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1426289058-6663-1-git-send-email-hali@codeaurora.org> References: <1426289058-6663-1-git-send-email-hali@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Prepare for initial DSI implementation Signed-off-by: Hai Li --- drivers/gpu/drm/msm/dsi/dsi.xml.h | 418 ++++++++++++++++++++++++++++++++++---- 1 file changed, 376 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h index abf1bba..1dcfae2 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -8,19 +8,10 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49) -- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20908 bytes, from 2014-12-08 16:13:00) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2357 bytes, from 2014-12-08 16:13:00) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 27208 bytes, from 2015-01-13 23:56:11) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) -- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 26848 bytes, from 2015-01-13 23:55:57) -- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 8253 bytes, from 2014-12-08 16:13:00) - -Copyright (C) 2013 by the following authors: +- /usr2/hali/local/envytools/envytools/rnndb/dsi/dsi.xml ( 18681 bytes, from 2015-03-04 23:08:31) +- /usr2/hali/local/envytools/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-01-28 21:43:22) + +Copyright (C) 2013-2015 by the following authors: - Rob Clark (robclark) Permission is hereby granted, free of charge, to any person obtaining @@ -51,11 +42,11 @@ enum dsi_traffic_mode { BURST_MODE = 2, }; -enum dsi_dst_format { - DST_FORMAT_RGB565 = 0, - DST_FORMAT_RGB666 = 1, - DST_FORMAT_RGB666_LOOSE = 2, - DST_FORMAT_RGB888 = 3, +enum dsi_vid_dst_format { + VID_DST_FORMAT_RGB565 = 0, + VID_DST_FORMAT_RGB666 = 1, + VID_DST_FORMAT_RGB666_LOOSE = 2, + VID_DST_FORMAT_RGB888 = 3, }; enum dsi_rgb_swap { @@ -69,20 +60,63 @@ enum dsi_rgb_swap { enum dsi_cmd_trigger { TRIGGER_NONE = 0, + TRIGGER_SEOF = 1, TRIGGER_TE = 2, TRIGGER_SW = 4, TRIGGER_SW_SEOF = 5, TRIGGER_SW_TE = 6, }; +enum dsi_cmd_dst_format { + CMD_DST_FORMAT_RGB111 = 0, + CMD_DST_FORMAT_RGB332 = 3, + CMD_DST_FORMAT_RGB444 = 4, + CMD_DST_FORMAT_RGB565 = 6, + CMD_DST_FORMAT_RGB666 = 7, + CMD_DST_FORMAT_RGB888 = 8, +}; + +enum dsi_lane_swap { + LANE_SWAP_0123 = 0, + LANE_SWAP_3012 = 1, + LANE_SWAP_2301 = 2, + LANE_SWAP_1230 = 3, + LANE_SWAP_0321 = 4, + LANE_SWAP_1032 = 5, + LANE_SWAP_2103 = 6, + LANE_SWAP_3210 = 7, +}; + #define DSI_IRQ_CMD_DMA_DONE 0x00000001 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002 #define DSI_IRQ_CMD_MDP_DONE 0x00000100 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200 #define DSI_IRQ_VIDEO_DONE 0x00010000 #define DSI_IRQ_MASK_VIDEO_DONE 0x00020000 +#define DSI_IRQ_BTA_DONE 0x00100000 +#define DSI_IRQ_MASK_BTA_DONE 0x00200000 #define DSI_IRQ_ERROR 0x01000000 #define DSI_IRQ_MASK_ERROR 0x02000000 +#define REG_DSI_6G_HW_VERSION 0x00000000 +#define DSI_6G_HW_VERSION_MAJOR__MASK 0xf0000000 +#define DSI_6G_HW_VERSION_MAJOR__SHIFT 28 +static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) +{ + return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK; +} +#define DSI_6G_HW_VERSION_MINOR__MASK 0x0fff0000 +#define DSI_6G_HW_VERSION_MINOR__SHIFT 16 +static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) +{ + return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK; +} +#define DSI_6G_HW_VERSION_STEP__MASK 0x0000ffff +#define DSI_6G_HW_VERSION_STEP__SHIFT 0 +static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) +{ + return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK; +} + #define REG_DSI_CTRL 0x00000000 #define DSI_CTRL_ENABLE 0x00000001 #define DSI_CTRL_VID_MODE_EN 0x00000002 @@ -96,11 +130,15 @@ enum dsi_cmd_trigger { #define DSI_CTRL_CRC_CHECK 0x01000000 #define REG_DSI_STATUS0 0x00000004 +#define DSI_STATUS0_CMD_MODE_ENGINE_BUSY 0x00000001 #define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002 +#define DSI_STATUS0_CMD_MODE_MDP_BUSY 0x00000004 #define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008 #define DSI_STATUS0_DSI_BUSY 0x00000010 +#define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000 #define REG_DSI_FIFO_STATUS 0x00000008 +#define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080 #define REG_DSI_VID_CFG0 0x0000000c #define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003 @@ -111,7 +149,7 @@ static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) } #define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030 #define DSI_VID_CFG0_DST_FORMAT__SHIFT 4 -static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_dst_format val) +static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) { return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; } @@ -129,21 +167,15 @@ static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) #define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000 #define REG_DSI_VID_CFG1 0x0000001c -#define DSI_VID_CFG1_R_SEL 0x00000010 -#define DSI_VID_CFG1_G_SEL 0x00000100 -#define DSI_VID_CFG1_B_SEL 0x00001000 -#define DSI_VID_CFG1_RGB_SWAP__MASK 0x00070000 -#define DSI_VID_CFG1_RGB_SWAP__SHIFT 16 +#define DSI_VID_CFG1_R_SEL 0x00000001 +#define DSI_VID_CFG1_G_SEL 0x00000010 +#define DSI_VID_CFG1_B_SEL 0x00000100 +#define DSI_VID_CFG1_RGB_SWAP__MASK 0x00007000 +#define DSI_VID_CFG1_RGB_SWAP__SHIFT 12 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) { return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK; } -#define DSI_VID_CFG1_INTERLEAVE_MAX__MASK 0x00f00000 -#define DSI_VID_CFG1_INTERLEAVE_MAX__SHIFT 20 -static inline uint32_t DSI_VID_CFG1_INTERLEAVE_MAX(uint32_t val) -{ - return ((val) << DSI_VID_CFG1_INTERLEAVE_MAX__SHIFT) & DSI_VID_CFG1_INTERLEAVE_MAX__MASK; -} #define REG_DSI_ACTIVE_H 0x00000020 #define DSI_ACTIVE_H_START__MASK 0x00000fff @@ -201,32 +233,115 @@ static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val) return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK; } -#define REG_DSI_ACTIVE_VSYNC 0x00000034 -#define DSI_ACTIVE_VSYNC_START__MASK 0x00000fff -#define DSI_ACTIVE_VSYNC_START__SHIFT 0 -static inline uint32_t DSI_ACTIVE_VSYNC_START(uint32_t val) +#define REG_DSI_ACTIVE_VSYNC_HPOS 0x00000030 +#define DSI_ACTIVE_VSYNC_HPOS_START__MASK 0x00000fff +#define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT 0 +static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val) { - return ((val) << DSI_ACTIVE_VSYNC_START__SHIFT) & DSI_ACTIVE_VSYNC_START__MASK; + return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK; } -#define DSI_ACTIVE_VSYNC_END__MASK 0x0fff0000 -#define DSI_ACTIVE_VSYNC_END__SHIFT 16 -static inline uint32_t DSI_ACTIVE_VSYNC_END(uint32_t val) +#define DSI_ACTIVE_VSYNC_HPOS_END__MASK 0x0fff0000 +#define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT 16 +static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val) { - return ((val) << DSI_ACTIVE_VSYNC_END__SHIFT) & DSI_ACTIVE_VSYNC_END__MASK; + return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK; +} + +#define REG_DSI_ACTIVE_VSYNC_VPOS 0x00000034 +#define DSI_ACTIVE_VSYNC_VPOS_START__MASK 0x00000fff +#define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT 0 +static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val) +{ + return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK; +} +#define DSI_ACTIVE_VSYNC_VPOS_END__MASK 0x0fff0000 +#define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT 16 +static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val) +{ + return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK; } #define REG_DSI_CMD_DMA_CTRL 0x00000038 +#define DSI_CMD_DMA_CTRL_BROADCAST_EN 0x80000000 #define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000 #define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000 #define REG_DSI_CMD_CFG0 0x0000003c +#define DSI_CMD_CFG0_DST_FORMAT__MASK 0x0000000f +#define DSI_CMD_CFG0_DST_FORMAT__SHIFT 0 +static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val) +{ + return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK; +} +#define DSI_CMD_CFG0_R_SEL 0x00000010 +#define DSI_CMD_CFG0_G_SEL 0x00000100 +#define DSI_CMD_CFG0_B_SEL 0x00001000 +#define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK 0x00f00000 +#define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT 20 +static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val) +{ + return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK; +} +#define DSI_CMD_CFG0_RGB_SWAP__MASK 0x00070000 +#define DSI_CMD_CFG0_RGB_SWAP__SHIFT 16 +static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val) +{ + return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK; +} #define REG_DSI_CMD_CFG1 0x00000040 +#define DSI_CMD_CFG1_WR_MEM_START__MASK 0x000000ff +#define DSI_CMD_CFG1_WR_MEM_START__SHIFT 0 +static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val) +{ + return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK; +} +#define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK 0x0000ff00 +#define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT 8 +static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val) +{ + return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK; +} +#define DSI_CMD_CFG1_INSERT_DCS_COMMAND 0x00010000 #define REG_DSI_DMA_BASE 0x00000044 #define REG_DSI_DMA_LEN 0x00000048 +#define REG_DSI_CMD_MDP_STREAM_CTRL 0x00000054 +#define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK 0x0000003f +#define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT 0 +static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val) +{ + return ((val) << DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK; +} +#define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 +#define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT 8 +static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val) +{ + return ((val) << DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK; +} +#define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK 0xffff0000 +#define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT 16 +static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val) +{ + return ((val) << DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK; +} + +#define REG_DSI_CMD_MDP_STREAM_TOTAL 0x00000058 +#define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK 0x00000fff +#define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT 0 +static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val) +{ + return ((val) << DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK; +} +#define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK 0x0fff0000 +#define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT 16 +static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val) +{ + return ((val) << DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK; +} + #define REG_DSI_ACK_ERR_STATUS 0x00000064 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } @@ -234,19 +349,25 @@ static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } #define REG_DSI_TRIG_CTRL 0x00000080 -#define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x0000000f +#define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x00000007 #define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0 static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val) { return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK; } -#define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x000000f0 +#define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x00000070 #define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT 4 static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val) { return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK; } -#define DSI_TRIG_CTRL_STREAM 0x00000100 +#define DSI_TRIG_CTRL_STREAM__MASK 0x00000300 +#define DSI_TRIG_CTRL_STREAM__SHIFT 8 +static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val) +{ + return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK; +} +#define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME 0x00001000 #define DSI_TRIG_CTRL_TE 0x80000000 #define REG_DSI_TRIG_DMA 0x0000008c @@ -274,6 +395,12 @@ static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010 #define REG_DSI_LANE_SWAP_CTRL 0x000000ac +#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007 +#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0 +static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val) +{ + return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK; +} #define REG_DSI_ERR_INT_MASK0 0x00000108 @@ -282,8 +409,36 @@ static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) #define REG_DSI_RESET 0x00000114 #define REG_DSI_CLK_CTRL 0x00000118 +#define DSI_CLK_CTRL_AHBS_HCLK_ON 0x00000001 +#define DSI_CLK_CTRL_AHBM_SCLK_ON 0x00000002 +#define DSI_CLK_CTRL_PCLK_ON 0x00000004 +#define DSI_CLK_CTRL_DSICLK_ON 0x00000008 +#define DSI_CLK_CTRL_BYTECLK_ON 0x00000010 +#define DSI_CLK_CTRL_ESCCLK_ON 0x00000020 +#define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200 + +#define REG_DSI_CLK_STATUS 0x0000011c +#define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000 #define REG_DSI_PHY_RESET 0x00000128 +#define DSI_PHY_RESET_RESET 0x00000001 + +#define REG_DSI_RDBK_DATA_CTRL 0x000001d0 +#define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000 +#define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16 +static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val) +{ + return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK; +} +#define DSI_RDBK_DATA_CTRL_CLR 0x00000001 + +#define REG_DSI_VERSION 0x000001f0 +#define DSI_VERSION_MAJOR__MASK 0xff000000 +#define DSI_VERSION_MAJOR__SHIFT 24 +static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) +{ + return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK; +} #define REG_DSI_PHY_PLL_CTRL_0 0x00000200 #define DSI_PHY_PLL_CTRL_0_ENABLE 0x00000001 @@ -501,5 +656,184 @@ static inline uint32_t REG_DSI_8960_LN_TEST_STR_1(uint32_t i0) { return 0x000003 #define REG_DSI_8960_PHY_CAL_STATUS 0x00000550 #define DSI_8960_PHY_CAL_STATUS_CAL_BUSY 0x00000010 +static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } + +static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } + +#define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100 + +#define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104 + +#define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108 + +#define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c + +#define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110 + +#define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114 + +#define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118 + +#define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c + +#define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120 + +#define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140 +#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff +#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144 +#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff +#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148 +#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff +#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c +#define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001 + +#define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150 +#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff +#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154 +#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff +#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158 +#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff +#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c +#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff +#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160 +#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff +#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164 +#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 +#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK; +} +#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 +#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168 +#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 +#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK; +} + +#define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c +#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff +#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 +static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) +{ + return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; +} + +#define REG_DSI_28nm_PHY_CTRL_0 0x00000170 + +#define REG_DSI_28nm_PHY_CTRL_1 0x00000174 + +#define REG_DSI_28nm_PHY_CTRL_2 0x00000178 + +#define REG_DSI_28nm_PHY_CTRL_3 0x0000017c + +#define REG_DSI_28nm_PHY_CTRL_4 0x00000180 + +#define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184 + +#define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188 + +#define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4 + +#define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8 + +#define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc + +#define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0 + +#define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4 + +#define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8 + +#define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4 + +#define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc + +#define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000 + +#define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004 + +#define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008 + +#define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c + +#define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010 + +#define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014 + +#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018 + #endif /* DSI_XML */ -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation