diff for duplicates of <1426920332-9340-14-git-send-email-sboyd@codeaurora.org> diff --git a/a/1.txt b/N1/1.txt index 25c08cb..1b041dc 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -21,7 +21,7 @@ index b3154c071652..a97cbec75abe 100644 + clock-latency = <100000>; }; - cpu@1 { + cpu at 1 { @@ -33,6 +36,9 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; @@ -31,7 +31,7 @@ index b3154c071652..a97cbec75abe 100644 + clock-latency = <100000>; }; - cpu@2 { + cpu at 2 { @@ -43,6 +49,9 @@ next-level-cache = <&L2>; qcom,acc = <&acc2>; @@ -41,7 +41,7 @@ index b3154c071652..a97cbec75abe 100644 + clock-latency = <100000>; }; - cpu@3 { + cpu at 3 { @@ -53,6 +62,9 @@ next-level-cache = <&L2>; qcom,acc = <&acc3>; @@ -268,37 +268,37 @@ index b3154c071652..a97cbec75abe 100644 #address-cells = <1>; #size-cells = <1>; @@ -122,21 +342,31 @@ - acc0: clock-controller@2088000 { + acc0: clock-controller at 2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu0_aux"; }; - acc1: clock-controller@2098000 { + acc1: clock-controller at 2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu1_aux"; }; - acc2: clock-controller@20a8000 { + acc2: clock-controller at 20a8000 { compatible = "qcom,kpss-acc-v1"; reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu2_aux"; }; - acc3: clock-controller@20b8000 { + acc3: clock-controller at 20b8000 { compatible = "qcom,kpss-acc-v1"; reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu3_aux"; + }; + -+ l2cc: clock-controller@2011000 { ++ l2cc: clock-controller at 2011000 { + compatible = "qcom,kpss-gcc"; + reg = <0x2011000 0x1000>; + clock-output-names = "acpu_l2_aux"; }; - saw0: regulator@2089000 { + saw0: regulator at 2089000 { diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index e1b0d5cd9e3c..ef89daf7a258 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -313,7 +313,7 @@ index e1b0d5cd9e3c..ef89daf7a258 100644 + }; - cpu@1 { + cpu at 1 { @@ -34,6 +38,10 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; @@ -366,25 +366,25 @@ index e1b0d5cd9e3c..ef89daf7a258 100644 #address-cells = <1>; #size-cells = <1>; @@ -101,11 +142,19 @@ - acc0: clock-controller@2088000 { + acc0: clock-controller at 2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu0_aux"; }; - acc1: clock-controller@2098000 { + acc1: clock-controller at 2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu1_aux"; + }; + -+ l2cc: clock-controller@2011000 { ++ l2cc: clock-controller at 2011000 { + compatible = "qcom,kpss-gcc"; + reg = <0x2011000 0x1000>; + clock-output-names = "acpu_l2_aux"; }; - saw0: regulator@2089000 { + saw0: regulator at 2089000 { diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index e265ec16a787..45ff96d74079 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -393,8 +393,8 @@ index e265ec16a787..45ff96d74079 100644 #size-cells = <0>; interrupts = <1 9 0xf04>; -- cpu@0 { -+ cpu0: cpu@0 { +- cpu at 0 { ++ cpu0: cpu at 0 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; @@ -406,8 +406,8 @@ index e265ec16a787..45ff96d74079 100644 + clock-latency = <100000>; }; -- cpu@1 { -+ cpu1: cpu@1 { +- cpu at 1 { ++ cpu1: cpu at 1 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; @@ -419,8 +419,8 @@ index e265ec16a787..45ff96d74079 100644 + clock-latency = <100000>; }; -- cpu@2 { -+ cpu2: cpu@2 { +- cpu at 2 { ++ cpu2: cpu at 2 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; @@ -432,8 +432,8 @@ index e265ec16a787..45ff96d74079 100644 + clock-latency = <100000>; }; -- cpu@3 { -+ cpu3: cpu@3 { +- cpu at 3 { ++ cpu3: cpu at 3 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; @@ -718,37 +718,37 @@ index e265ec16a787..45ff96d74079 100644 }; }; -+ clock-controller@f9016000 { ++ clock-controller at f9016000 { + compatible = "qcom,hfpll"; + reg = <0xf9016000 0x30>; + clock-output-names = "hfpll_l2"; + }; + -+ clock-controller@f908a000 { ++ clock-controller at f908a000 { + compatible = "qcom,hfpll"; + reg = <0xf908a000 0x30>, <0xf900a000 0x30>; + clock-output-names = "hfpll0"; + }; + -+ clock-controller@f909a000 { ++ clock-controller at f909a000 { + compatible = "qcom,hfpll"; + reg = <0xf909a000 0x30>, <0xf900a000 0x30>; + clock-output-names = "hfpll1"; + }; + -+ clock-controller@f90aa000 { ++ clock-controller at f90aa000 { + compatible = "qcom,hfpll"; + reg = <0xf90aa000 0x30>, <0xf900a000 0x30>; + clock-output-names = "hfpll2"; + }; + -+ clock-controller@f90ba000 { ++ clock-controller at f90ba000 { + compatible = "qcom,hfpll"; + reg = <0xf90ba000 0x30>, <0xf900a000 0x30>; + clock-output-names = "hfpll3"; + }; + - saw_l2: regulator@f9012000 { + saw_l2: regulator at f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; -- diff --git a/a/content_digest b/N1/content_digest index 15d5a46..8665114 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,14 +1,8 @@ "ref\01426920332-9340-1-git-send-email-sboyd@codeaurora.org\0" - "From\0Stephen Boyd <sboyd@codeaurora.org>\0" + "From\0sboyd@codeaurora.org (Stephen Boyd)\0" "Subject\0[PATCH v3 13/13] ARM: dts: qcom: Add necessary DT data for Krait cpufreq\0" "Date\0Fri, 20 Mar 2015 23:45:32 -0700\0" - "To\0Mike Turquette <mturquette@linaro.org>" - " Stephen Boyd <sboyd@codeaurora.org>\0" - "Cc\0linux-kernel@vger.kernel.org" - linux-arm-msm@vger.kernel.org - linux-pm@vger.kernel.org - linux-arm-kernel@lists.infradead.org - " Viresh Kumar <viresh.kumar@linaro.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Add the necessary DT nodes and data so we can probe the cpufreq\n" @@ -34,7 +28,7 @@ "+\t\t\tclock-latency = <100000>;\n" " \t\t};\n" " \n" - " \t\tcpu@1 {\n" + " \t\tcpu at 1 {\n" "@@ -33,6 +36,9 @@\n" " \t\t\tnext-level-cache = <&L2>;\n" " \t\t\tqcom,acc = <&acc1>;\n" @@ -44,7 +38,7 @@ "+\t\t\tclock-latency = <100000>;\n" " \t\t};\n" " \n" - " \t\tcpu@2 {\n" + " \t\tcpu at 2 {\n" "@@ -43,6 +49,9 @@\n" " \t\t\tnext-level-cache = <&L2>;\n" " \t\t\tqcom,acc = <&acc2>;\n" @@ -54,7 +48,7 @@ "+\t\t\tclock-latency = <100000>;\n" " \t\t};\n" " \n" - " \t\tcpu@3 {\n" + " \t\tcpu at 3 {\n" "@@ -53,6 +62,9 @@\n" " \t\t\tnext-level-cache = <&L2>;\n" " \t\t\tqcom,acc = <&acc3>;\n" @@ -281,37 +275,37 @@ " \t\t#address-cells = <1>;\n" " \t\t#size-cells = <1>;\n" "@@ -122,21 +342,31 @@\n" - " \t\tacc0: clock-controller@2088000 {\n" + " \t\tacc0: clock-controller at 2088000 {\n" " \t\t\tcompatible = \"qcom,kpss-acc-v1\";\n" " \t\t\treg = <0x02088000 0x1000>, <0x02008000 0x1000>;\n" "+\t\t\tclock-output-names = \"acpu0_aux\";\n" " \t\t};\n" " \n" - " \t\tacc1: clock-controller@2098000 {\n" + " \t\tacc1: clock-controller at 2098000 {\n" " \t\t\tcompatible = \"qcom,kpss-acc-v1\";\n" " \t\t\treg = <0x02098000 0x1000>, <0x02008000 0x1000>;\n" "+\t\t\tclock-output-names = \"acpu1_aux\";\n" " \t\t};\n" " \n" - " \t\tacc2: clock-controller@20a8000 {\n" + " \t\tacc2: clock-controller at 20a8000 {\n" " \t\t\tcompatible = \"qcom,kpss-acc-v1\";\n" " \t\t\treg = <0x020a8000 0x1000>, <0x02008000 0x1000>;\n" "+\t\t\tclock-output-names = \"acpu2_aux\";\n" " \t\t};\n" " \n" - " \t\tacc3: clock-controller@20b8000 {\n" + " \t\tacc3: clock-controller at 20b8000 {\n" " \t\t\tcompatible = \"qcom,kpss-acc-v1\";\n" " \t\t\treg = <0x020b8000 0x1000>, <0x02008000 0x1000>;\n" "+\t\t\tclock-output-names = \"acpu3_aux\";\n" "+\t\t};\n" "+\n" - "+\t\tl2cc: clock-controller@2011000 {\n" + "+\t\tl2cc: clock-controller at 2011000 {\n" "+\t\t\tcompatible = \"qcom,kpss-gcc\";\n" "+\t\t\treg = <0x2011000 0x1000>;\n" "+\t\t\tclock-output-names = \"acpu_l2_aux\";\n" " \t\t};\n" " \n" - " \t\tsaw0: regulator@2089000 {\n" + " \t\tsaw0: regulator at 2089000 {\n" "diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi\n" "index e1b0d5cd9e3c..ef89daf7a258 100644\n" "--- a/arch/arm/boot/dts/qcom-msm8960.dtsi\n" @@ -326,7 +320,7 @@ "+\n" " \t\t};\n" " \n" - " \t\tcpu@1 {\n" + " \t\tcpu at 1 {\n" "@@ -34,6 +38,10 @@\n" " \t\t\tnext-level-cache = <&L2>;\n" " \t\t\tqcom,acc = <&acc1>;\n" @@ -379,25 +373,25 @@ " \t\t#address-cells = <1>;\n" " \t\t#size-cells = <1>;\n" "@@ -101,11 +142,19 @@\n" - " \t\tacc0: clock-controller@2088000 {\n" + " \t\tacc0: clock-controller at 2088000 {\n" " \t\t\tcompatible = \"qcom,kpss-acc-v1\";\n" " \t\t\treg = <0x02088000 0x1000>, <0x02008000 0x1000>;\n" "+\t\t\tclock-output-names = \"acpu0_aux\";\n" " \t\t};\n" " \n" - " \t\tacc1: clock-controller@2098000 {\n" + " \t\tacc1: clock-controller at 2098000 {\n" " \t\t\tcompatible = \"qcom,kpss-acc-v1\";\n" " \t\t\treg = <0x02098000 0x1000>, <0x02008000 0x1000>;\n" "+\t\t\tclock-output-names = \"acpu1_aux\";\n" "+\t\t};\n" "+\n" - "+\t\tl2cc: clock-controller@2011000 {\n" + "+\t\tl2cc: clock-controller at 2011000 {\n" "+\t\t\tcompatible = \"qcom,kpss-gcc\";\n" "+\t\t\treg = <0x2011000 0x1000>;\n" "+\t\t\tclock-output-names = \"acpu_l2_aux\";\n" " \t\t};\n" " \n" - " \t\tsaw0: regulator@2089000 {\n" + " \t\tsaw0: regulator at 2089000 {\n" "diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi\n" "index e265ec16a787..45ff96d74079 100644\n" "--- a/arch/arm/boot/dts/qcom-msm8974.dtsi\n" @@ -406,8 +400,8 @@ " \t\t#size-cells = <0>;\n" " \t\tinterrupts = <1 9 0xf04>;\n" " \n" - "-\t\tcpu@0 {\n" - "+\t\tcpu0: cpu@0 {\n" + "-\t\tcpu at 0 {\n" + "+\t\tcpu0: cpu at 0 {\n" " \t\t\tcompatible = \"qcom,krait\";\n" " \t\t\tenable-method = \"qcom,kpss-acc-v2\";\n" " \t\t\tdevice_type = \"cpu\";\n" @@ -419,8 +413,8 @@ "+\t\t\tclock-latency = <100000>;\n" " \t\t};\n" " \n" - "-\t\tcpu@1 {\n" - "+\t\tcpu1: cpu@1 {\n" + "-\t\tcpu at 1 {\n" + "+\t\tcpu1: cpu at 1 {\n" " \t\t\tcompatible = \"qcom,krait\";\n" " \t\t\tenable-method = \"qcom,kpss-acc-v2\";\n" " \t\t\tdevice_type = \"cpu\";\n" @@ -432,8 +426,8 @@ "+\t\t\tclock-latency = <100000>;\n" " \t\t};\n" " \n" - "-\t\tcpu@2 {\n" - "+\t\tcpu2: cpu@2 {\n" + "-\t\tcpu at 2 {\n" + "+\t\tcpu2: cpu at 2 {\n" " \t\t\tcompatible = \"qcom,krait\";\n" " \t\t\tenable-method = \"qcom,kpss-acc-v2\";\n" " \t\t\tdevice_type = \"cpu\";\n" @@ -445,8 +439,8 @@ "+\t\t\tclock-latency = <100000>;\n" " \t\t};\n" " \n" - "-\t\tcpu@3 {\n" - "+\t\tcpu3: cpu@3 {\n" + "-\t\tcpu at 3 {\n" + "+\t\tcpu3: cpu at 3 {\n" " \t\t\tcompatible = \"qcom,krait\";\n" " \t\t\tenable-method = \"qcom,kpss-acc-v2\";\n" " \t\t\tdevice_type = \"cpu\";\n" @@ -731,41 +725,41 @@ " \t\t\t};\n" " \t\t};\n" " \n" - "+\t\tclock-controller@f9016000 {\n" + "+\t\tclock-controller at f9016000 {\n" "+\t\t\tcompatible = \"qcom,hfpll\";\n" "+\t\t\treg = <0xf9016000 0x30>;\n" "+\t\t\tclock-output-names = \"hfpll_l2\";\n" "+\t\t};\n" "+\n" - "+\t\tclock-controller@f908a000 {\n" + "+\t\tclock-controller at f908a000 {\n" "+\t\t\tcompatible = \"qcom,hfpll\";\n" "+\t\t\treg = <0xf908a000 0x30>, <0xf900a000 0x30>;\n" "+\t\t\tclock-output-names = \"hfpll0\";\n" "+\t\t};\n" "+\n" - "+\t\tclock-controller@f909a000 {\n" + "+\t\tclock-controller at f909a000 {\n" "+\t\t\tcompatible = \"qcom,hfpll\";\n" "+\t\t\treg = <0xf909a000 0x30>, <0xf900a000 0x30>;\n" "+\t\t\tclock-output-names = \"hfpll1\";\n" "+\t\t};\n" "+\n" - "+\t\tclock-controller@f90aa000 {\n" + "+\t\tclock-controller at f90aa000 {\n" "+\t\t\tcompatible = \"qcom,hfpll\";\n" "+\t\t\treg = <0xf90aa000 0x30>, <0xf900a000 0x30>;\n" "+\t\t\tclock-output-names = \"hfpll2\";\n" "+\t\t};\n" "+\n" - "+\t\tclock-controller@f90ba000 {\n" + "+\t\tclock-controller at f90ba000 {\n" "+\t\t\tcompatible = \"qcom,hfpll\";\n" "+\t\t\treg = <0xf90ba000 0x30>, <0xf900a000 0x30>;\n" "+\t\t\tclock-output-names = \"hfpll3\";\n" "+\t\t};\n" "+\n" - " \t\tsaw_l2: regulator@f9012000 {\n" + " \t\tsaw_l2: regulator at f9012000 {\n" " \t\t\tcompatible = \"qcom,saw2\";\n" " \t\t\treg = <0xf9012000 0x1000>;\n" "-- \n" "The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\n" a Linux Foundation Collaborative Project -e6cc628422f9e4be887b12f5b7dc8a97f4b031b247b52b4c77a95ffe816f7865 +af17ac9e1c15cf4f39ce91ae120fd7dd622d85563652955fdc4e7780f2c76ea0
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